The rise/fall times are not that critical, no. As shown in the data sheet for the device you reference:
Referring to Figure 33, the clock signal alternatively switches
the SHA between sample mode and hold mode. When the SHA
is switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle.
So it is not how fast it switches from LOW to HIGH or HIGH to LOW, but how long it remains in that steady state, and how stable your signal is during that state.
Basically, when the clock is HIGH the SHA capacitor is "reading" the analogue signal. When the clock is LOW the SHA capacitor is isolated from the analogue signal, and its voltage is presented to the sampling pipelines for conversion.
Obviously you want to read the value from that capacitor before it decays too much, so an overly huge fall time could be detrimental, but in general the rise and fall times are dwarfed by the required minimum level times (6.2ns to 15ns depending on model). There is no stated maximum time, only a minimum sample rate of 1MSPS, so a maximum clock period of 1µs, or a rise + hold or fall + hold maximum time of 500ns (with the previously stated minimum hold time) by my calculations.
The SHA capacitor effectively looks a little like a low-pass filter, with a time constant equal to the SHA charge time. For one of the devices that is 6.2ns, but others are as much as 15ns.
So the value in the SHA capacitor is effectively like a weighted rolling average of the past 6.2ns of voltages, and the final value is taken at the moment the ADC switches from SAMPLE to HOLD. Therefore you should ensure that the falling edge if the sampling clock occurs during a period where your sampled signal is stable, as it's the end of the sampling period, not the start that gives you your final value.
From your given waveforms, the TRIG signal falls during a trough in the video waveform. The sampled value would therefore be influenced by that trough and the results would be low. The SAMP signal, as the inverse, falls during one of the stable 2.5V periods, and that has been stable for more than 6.2ns, so would give a much more reliable reading of the 2.5V level.
When you toggle a pin at a certain rate, the resulting waveform will have a frequency at half of the toggle rate. So if your output waveform was a 8kHz square wave, then your ADC sample rate is actually 16kHz, which explains the factor of 2 error.
Best Answer
Many ADC input circuits will connect a capacitor with an unpredictable charge state to the input they're about to sample. If the input is a very low impedance source and won't "budge", this won't pose a problem; that capacitance will quickly match the voltage on the input. If the input is a moderate-impedance source but has very low capacitance, connecting that capacitance may disturb the voltage on the input, but the voltage on the input will relatively quickly return to the correct value. If the input is a high- or moderate-impedance source and has a huge amount of capacitance of its own (e.g. for a 12-bit ADC, it exceeds the sampling capacitance of the ADC by a factor of a few thousand), and if readings are not taken too frequently, the big capacitor may be considered a low-impedance source that won't "budge". If, however, the input has a capacitance that is e.g. 50 times the input sampling cap, then connecting the sampling cap may disturb the input voltage by 1/50 of full scale (a big disturbance) but the increased capacitance may increase 50-fold the RC time constant for its returning to normal.
If the ADC waits long enough between connecting the input capacitance and taking a reading, any disturbance caused by switching the input capacitance will likely settle out. On the other hand, there are some situations where such settling time isn't needed but rapid readings are. Making the acquisition time programmable allows both types of situations to be accommodated.