Method 1: Create ROMs in your FPGA design
Because you have the same data in every board, one option is to use block RAMs in the FPGA, configured as ROM. To do this you instantiate a block RAM, but don't connect to the write pins. Use a synthesis directive in your HDL code or UCF file to specify the initial contents of the RAM. Read the Spartan-3 Generation User's Guide (Chapter 4) to see how to instantiate the RAM and how to access the data from the RAM. If you use Xilinx ISE, there is probably also a "wizard" to generate the RAM block and set up the initial contents for you.
Unfortunately, the Spartan-3E you are using has only 350 kbits of block RAM, not 8 Mbits like you require. For this to work then, you'll have to work out a scheme to compress your data to fit in 350 kbits. The details of how to do this depend on what kind of data you have. If your data is especially random, it might not be reasonable to get this much compression.
Method 2: Store data in external memory
You say you have a 128 Mbit parallel flash and a 16 Mbit SPI flash. You will need to read the datasheets for these parts and understand how they work. Then write a state machine into your FPGA that can access these devices. But this is your job as the FPGA designer. Some random strangers on the internet are not going to design your FPGA for you.
To store the data onto the flash initially you have two choices. First would be, if you are building these boards in volume, you can have your board assembly shop pre-program the flash devices before assembling them onto the boards. Typically you give them a data file in some format they request, and they charge you some small extra fee to have the data flashed in before assembly.
Second option: Read the datasheet for the flash device. Write an FPGA design that allows you to send data from some other interface available on your board (Ethernet, USB, SPI, I2C, whatever), and load it into the flash. At manufacturing time, you load this design temporarily into your FPGA and program your flash; then you store a different "run-time" FPGA design into the on-board configuration PROM, that doesn't have the ability to modify the FLASH, and your users won't have the ability to mess up the data.
In this case, it's intellectual property. When you design something in an FPGA, that design is considered intellectual property. So the term IP is just used generically for any kind of 'firmware' you write into an FPGA. In this case, you could either design (or buy) an IP implementation, of use their hardware one.
Best Answer
A traffic generator in this context is simply something that generates traffic on the memory interface.
It isn't a specific thing, it could be just a counter generating addresses and read and write signals, or test patterns to run memory tests, or random numbers.
In the context of a user design, it is simply that part of the overall design which uses the MIG interface - you could view the entire rest of your FPGA design as a Traffic Generator.
One way to define your own is to build a CPU based system that needs to access memory through the MIG interface.
As to being necessary; it's the other way around. If you don't have a Traffic Generator in your design, there is nothing that needs to access memory, so you don't need the MIG.