Electronic – Transistor pad layout for efficient use of prober

padstestingtransistors

As we are a materials company the expertise is not in EE, so I am asking a very simple question. I tried to search online for this, but could not find an answer. We are making transistors with our special materials and need to put many on a test chip. Hooking each one of them up with their own pads we quickly run out of pads and are limited to fewer devices.

What strategies exist to "chain" the structures together to share pads? What risks are there in doing this?

See the example of the four transistors that use 12 pads to test. Can the source and/or drain be one common pad and only need to change the tester for the gate?

Any references that would be helpful would be greatly appreciated.

Thanks.

Four transistors to be tested

Best Answer

Any time you add probe pads, you're sacrificing the density of test devices. The density you end up with depends on how accurately you can probe, how small a probe pad you can make, and how many terminals on your transistor you can share.

A word of caution, make sure you know what the minimum pitch and pad size you can probe effectively is using your equipment. It does you no good to have twice as many structures to test if it takes you much longer to land probes.

From a typical 4 terminal device perspective, the main question is how many pads can you save by tying them together, and what can go wrong.

  • Body/Substrate: usually safe to connect together. Exceptions include cases where you expect a significant leakage current from any other terminal to the substrate.
  • Source: usually safe to connect together. You give up the ability to measure source to substrate leakage/diode of an individual device when the source voltage is different from the substrate. The RDSon of your MOSFET should be much larger than your metal resistance, or else it will impact your measurement.
  • Gate: This one is really tempting to short together, but it is also a dangerous one. As long as your gate current is effectively zero, like in a traditional MOSFET, you can get away with shorting gates. If you have limited isolation to your channel, like in a MESFET, JFET, or HEMT, then you should probably pass. My experience has been that a shared gate test structure fails in difficult to detect ways, and can subtly change measurements. Consider the case where you have 10 transistors in a structure with substrate, source, and gate shorted. If one of the gates has failed short, it will reduce the gate voltage seen by all 10 transistors, without giving any indication other than gate current. In that case, all 10 devices are unusable even though only 1 failed. Device failure can come from manufacturing yield or electrical over stress, and ESD protection is typically omitted in these structures.
  • Drain: shorting these instead of the gates is not a good idea. You would need to actively drive every gate, even those not in use. The drain current, which is one of the primary measurements, always will have IDSoff of all devices combined in parallel. Don't do this.

My preference would be to have as few shorted terminals as possible. Shorting the source is relatively low risk, but higher current measurements will suffer. Shorting all gates and shorting all sources is something I wouldn't do for anything more than a process monitoring structure, preferably not for device characterization.

Keysight has a pretty good book on transistor characterization from the measurement perspective: The Parametric Measurement Handbook. There's a lot of good general information, and there's a decent amount of up-selling a $100-500k semiconductor parameter measurement tool.

Related Topic