I'm studying Jim Williams application note AN-104 – Load Transient Response Testing for Voltage Regulators, in which he describes an FET-based load transient generator, what might commonly be called an electronic load or dummy load.
In the highlighted areas, Jim mentions "peaking" components:
And apparently, when properly adjusted, these peaking trimmers allow the circuit to produce a very clean-edged and flat output (current through the MOSFET, trace B):
Note the LT1210 is a current feedback amplifier, not one of the perhaps more familiar voltage feedback variety.
My question is: "What is the peaking Jim is talking about here and how does trimming it optimize this circuit's output waveform?"
I vaguely suspect it has something to do with adjusting the resonant frequency of the gate drive node (and separately the feedback network) to push just the right amount of charge into the MOSFET gate at the fastest possible speed, but really don't have much of a clue 🙂
Best Answer
This comes down to the amplifier, and is perhaps best illustrated by the gain characteristics into a capacitive load:
The flattest curve is when Rf is somewhere around 1.5k, and that is what is in the load circuit (1k trim, 560 ohm fixed), As the circuit will vary with parts (particularly the amplifier and FET), this needs to be trimmed for flattest response. Note that this trim is for capacitive load peaking (or in reality, de-peaking).
The loop peaking trim sets the loop gain for transient response.
This amplifier (ignoring DC offset for now) is a follower at steady state, but has some gain for transient performance (Rg is only effectively in circuit for transient events). To get just the right gain for fast loop performance, but maintaining low peaking of the gain performance, this ac gain needs to be adjustable as well; hence the loop peaking adjustment.
Note that the graph shows best peaking compensation performance at a gain of 6dB, and the Rf and Rg values show the gain will be somewhere in this ballpark area.
The gate drive peaking is to adjust the current available by limiting to just enough drive; this gives sufficient drive to drive the FET, but limits the effect of gate capacitance to a manageable level.
All these adjustments are simply because driving a power FET gate requires some compensation to account for capacitive loading, and is why these are not present in the subsequent bipolar circuit.
The 2.5Ω resistor and 10μF ceramic device appear to be the damping circuit referred to in the text.