Electronic – Truth Table Accuracy

First: let's assume that the truth table values are calculated for the rising edge of the clock. This is sequential logic, and the truth tables requires informations about the previous state; in this case, Z represents Q(i-1).

There are some mistakes in the truth table, but the truth table of the full adder is this:

$$ X+Y+Z=1 \rightarrow Q=0, S=1 $$

$$ X+Y+Z=2 \rightarrow Q=1, S=0 $$

$$ X+Y+Z=3 \rightarrow Q=1, S=1 $$

The flip-flop is used to keep the old carry output until the clock is raised (and to avoid the loop due to the feedback to the carry input), and it doesn't change the truth table as long as you consider the values after the edge.

So, this should be a (clocked) serial adder, because inputing two sequences of bits (starting from the less weighted) after resetting Q, you have at the output S the equivalent bit of their binary sum.

IMPORTANT: You should latch the sum bit because otherwise when you have the rising edge, the sum will be updated with the new value of the carry, so will be valid only until the carry signal is passed through the adder.

In this case, in which the sum bit is not latched, it will assume a value that takes into account the carry of the new operation, and it won't be correct; so the truth table will be like this:

Z  Y  X  |  Q  S
----------------
0  0  0  |  0  0
0  0  1  |  0  1
0  1  0  |  0  1
0  1  1  |  1  1  !
1  0  0  |  0  1
1  0  1  |  1  0
1  1  0  |  1  0
1  1  1  |  1  1

! := It's not the value that an adder would give, because with the clock raising edge, the carry out is brought to Q and sums with X and Y giving again the sum and carry high.