I haven't used Altera, or the FIFO you are using, and the signals you have in your picture makes no sense to me. But I have designed many FIFO's and maybe I can still give some insight into what you are seeing...
Many FIFO's have a strange notion of "full". Specifically, "full" is when there is one less words than what you think there should be. A 16-word deep FIFO can only hold 15 words. Or a 64 word FIFO can really only hold 63 words. In these FIFO's, the RAM used is 16 or 64 words but the logic used to calculate the full-ness will signal FULL at one less. Attempting to put 16 or 64 words into that FIFO will result in bad stuff. Not every FIFO is like this, but most of them are.
Some FIFO's, particularly ones with a separate read and write clock, will take time for data written to it to appear on the read port. Sometimes a surprising amount of time. To put it a different way... Let's say that the FIFO is completely empty, and you start writing to the FIFO as fast as possible. You might be able to write several words to the FIFO before the "FIFO Not Empty" signal goes active. This means that you can't start emptying the FIFO until later than you might expect. Which means that you might have more words in the FIFO than you anticipated. Which could cause it to fill up.
The length of time for a written word to appear on the read port varies depending on the internal architecture of the FIFO. Sometimes it is within a clock cycle. Other FIFO's could require several write-clocks plus several read-clocks.
Requiring several write-clocks and/or several read-clocks brings up an interesting issue. There are many FIFO's which don't behave well with discontinuous clocks. That is, a clock that just isn't continuously running. If it takes 3 read-clocks to bring the write data to the read port, and you only give it 2 clocks then the data is not going to get there. The data will accumulate in the FIFO and never get read. You can actually get into a state where the FIFO claims to be both empty and full at the same time! Empty, because the data has not gotten to the read port yet. And full, because there is no more room in the RAM to write new data.
So, those are some reasons why the full flag might be going active when you don't expect it to. But you must also consider that you are just doing something else wrong. There's a bug in your code, or you have a noisy clock, or you have incorrect timing constraints. Those are real possibilities that I can't diagnose remotely.
The FIFO reduces the number of interrupts the attached processor has to service. In theory you could bypass it, but if you do so, the microprocessor will typically waste a lot of time on the overhead of interrupt servicing.
For a quick analogy, let's assume you were asked to move 40 gallons of water 20 miles. The FIFO is roughly equivalent to a truck with a 20 gallon water tank, so you make only two trips to get all the water to the destination. Without the FIFO, you can only carry one water bottle at a time, so you'd have to make around 500 trips back and forth instead.
Best Answer
A FIFO is a First In First Out memory. You can think of data being shifted in one end and shifted out the other, with the amount of data in the FIFO being allowed to grow up to some maximum limit.
However, actually shifting data around in memory is costly to do in hardware. A better way is to use a memory more normally but make it look like a circular buffer by manipulation of the next address to write to and read from. These addresses live in separate registers, and are often called the read pointer and the write pointer.
Here is a illustration of the state for a simple FIFO using a 8-word memory:
The next incoming word will be written to the empty word at address 1 (the value of the write pointer), then the write pointer incremented to 2. The next read request will fetch the word at 5 (the value of the read pointer), then the read pointer is incremented by 1. In this example, the addresses are automatically circular if the pointers are 3 bits wide. Adding 1 to 7 yields 0 in 3-bit unsigned math.
Complete FIFO systems need ways to indentify the full and empty conditions. There are various schemes for this. A separate register could be used to keep track of how many words are in the FIFO, which is 4 in the snapshot shown above.
A useful scheme for a firmware implementation is to compare the read and write pointers. You could, for example, decide that both pointers equal is FIFO empty, and write one behind read (after wrapping) is FIFO full. Note that such schemes will leave one word of the FIFO unused. You end up spending a piece of state somewhere to allow detection of full and empty, whether that's a separate register or a unusable word in the FIFO. The advantage of this scheme is that reads and writes can happen independently without conflict, so such a FIFO doesn't need a mutex between reading and writing. For example, you don't have to disable interrupts when reading because no harm is done if a interrupt routine pushes a word onto the FIFO while foreground code is trying to read.