I am working on a low frequency 30 khz module that needs to have an ultra low power consumption. The problem is the research focuses on improving the performance of the adders and multiplier and doesn't focus on the power consumption.
Could some one tell me what are the best architectures for multipliers and adders to have the lowest power consumption in nW?
Let me put my question in an other form: What is the adder and multiplier architecture that achieves the lowest power consumption so I can build them using vhdl, knowing that the delay is not an important issue.
Best Answer
Try looking into bit serial logic. It's slow, but small and thus the instant power use would be low.