mosfetsimulation
I made a simple simulation of following circuit (in LTSpice):
The IRFZ44N mosfet (10v on gate voltage) is switched on and off with 1kHZ 12V 50% duty cycle PWM signal. The "Heavy-load" is just a passive, 1 Ohm resistor.
I got following simulation result:
Why does the vout voltage reach just 7V (I expected something around 12V, since fet should be fully on)? Why is the load current (I heavy load) so much non-linear curved cycle?
Here's a circuit I did a few years ago that demonstrates a driver chip local to the MOSFET and an over-current protection in case the load shorted out. The MOSFET used is not as suitable as the BUK954 you mentioned on another question. I'd use that type for your job.
The load is assumed to be purely resistive. In fact the original circuit had two MOSFETs driving a transformer with a centre-tap to the positive supply rail and it didn't need fly-back diodes (it used snubbers) but your's might need a protection diode across the load.
Circled in red is a local +5V power rail used for the over-current monitor - this can easily be derived locally with a small linear regulator such as 78L05.
Also note the big array of capacitors to the left of the circuit that absorbs most of the transient energy locally produced by switching the load. The original design was switching at 600kHz so if you wanted to run faster than 20kHz this shouldn't be a problem but i wouldn't go above 100kHz for the sake of efficiency.
The reason the FET turns off so slowly is because you only have 2 kΩ pulling it high. Take a look at the datasheet for that FET. It should show you the actual and effective gate capacitance when switching. The relatively weak 2 kΩ pullup is working against that capacitance.
Here is a trick I sometimes use in this situation:
The double emitter follower is basically a impedance buffer. The current to charge and discharge the gate capacitance is handled by Q1 and Q2, so the signal at GATE can be much higher impedance and still switch the FET quickly. Note that this double emitter follower will loose 700 mV or so on each end. That is fine for a FET that switches over a 10 V gate range. It will still be "off" with 700 mV on the gate just as well as with 0. At the other end, its usually easy enough to drive GATE the extra 700 mV further than what you want to make sure shows up on the gate of Q3.
Best Answer
You have put the load in the source; as the gate voltage must be above the source by a few volts to switch the device on (N channel enhancement mode MOSFET), the source cannot rise above (in this case) 7V. As the source voltage approaches \$V_{gs}\$ at a level to support 7A, it simply cannot drive any harder.
If you put the load between the drain and the 12V power and tie the source to ground, you should get the results you expect.
Here is a circuit that implements it, and it simulates as I would expect:
The plot:
The simulation model must be in the same directory as the simulation circuit; make sure you set up the FET properly:
Hover the cursor over the FET and CTRL Right click to get this:
It is important that the prefix is 'X' as this indicates to LTSpice that the model is a subckt.