I am little bit confused about the requirements of USB 2.0 high-speed.
USB 2.0. high-speed maximum transfer rate is 480 Mbit/s. So from my understanding to fully utilize this data rate one should use IC(uC or FPGA) with frequency at least 480 MHz.
But for example STM32 F4 series microcontroller provide USB 2.0 high-speed support, though the maximum frequency they run on is 180 MHz.
Also Atmel SAM3U supports high-speed USB, despite absolute maximum frequency of 192 MHz.
How is that?
For Atmel I noticed they have additional clock of 480 MHz just for USB. This is even more confusing, since if microcontroller is capable only of 192 MHz -how it should communicate with internal USB periheral that runs on 480 MHz?
For STM32 it is also weird, in their CubeMX software it seems they run USB from 48 MHz clock. Searching datasheet, only mention I found was
Bit 15 PHYLPCS:
PHY Low-power clock select
This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the
PHY can usually operate on a 48 MHz clock to save power.
0: 480 MHz internal PLL clock
1: 48 MHz external clock
In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates
at 48 MHz in FS and LS modes.
So I suppose it uses 48 MHz clock to generate 480 MHz through PLL.
But again – if microcontroller itself can only go up to 180 MHz – what is the point of 480 MHz USB?
FPGAs are even more confusing(many run below 480 MHz), but I haven't done much research on FPGA yet, so I will not ask anything(but if you can give some advice/educate about FPGA – you are welcome, I am interested).
The question is – if we use 180 MHz microcontroller and want to transfer data with 480 MHz usb peripheral – how does it match the frequency? What is the process?
Best Answer
Please note that USB is 480M bits per second, while uPs have their data usually 8 or 32 bit wide. So the rate of system data transfer goes down to 60MHz or 15Mhz only. USB controllers use hardware access to uP memory (aka direct memory access, or "bus mastering") to transfer blocks of data between the system memory and USB PHY (Physical layer transceiver). The transfers are done in 8 or 16-bit parallel format, and the PHY performs parallel-to-serial conversion. The system usually has plenty of "elasticity" buffers (FIFOs) to provide coherent USB packets in full accords with specified data rates.
The rate of how fast a system can prepare the read/write memory buffers depends on overall processor throughput, so low-performing processors might not achieve maximum USB throughput.