Electronic – use a common Clock pin on the micro-controller project instead of separate clock pins

If both of your microcontrollers support setting the pins you are using as the serial clock signal to a high impedance state/tristate (if you are using a normal GPIO pin most micros would support this) then you can achieve what you have described without any additional components or insulating the clock pins from each other. What you will be doing is just directly wiring the two micro clock pins and the shift register's clock input together, then setting each micro's serial clock pin to high impedance whenever it is not actively generating a clock signal, leaving the other micro free to drive the clock line. There is an older question covers what it means to set a pin to high impedance/tristate a pin.

As you've picked up on with asking about 'insulating' the clock lines from each other, you want to tristate the pins so that there is not 'contention' when one micro is trying to drive the clock signal line in one direction (eg. high) and the other micro is trying to drive it in another direction (eg. low) - which would cause the two micros to source/sink a lot of current, get things hot, potentially let the magic smoke escape and generally cause trouble. As a result you should be careful that there is never any time when both micros are actively driving (ie. not high impedance) the clock line at the same time, particularly during the hand-over time when you are changing which micro is driving the clock line.

You will probably also want to add a pull up resistor on the shared clock line to avoid the clock line being free to oscillate around due to any noise it picks up at times when neither micro is actively driving the line (ie. both have their clocks set to high impedance - this will probably happen, at least for a short time, if you pay attention to the previous sentence...). You may be able to get away without the pull up resistor by using the internal pull ups on the micros, or just get lucky and not pick up any 'spurious' clock signals, but it would be safer to add the external pull up.

The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA.

If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the entire chip!). Instantiating logic which passes a signal from combinational logic to a clock will typically result in one of these networks being used for that signal, making it unavailable for other logic on the chip.

To avoid this, most FPGAs will make logic primitives available with separate combinational logic "enable" signals. (Xilinx calls theirs FDCE/FDPE/FDRE/FDSE depending on the state at reset, and Altera calls theirs DFFE.) These logic elements will (more or less) AND the clock signal with the combinational enable signal, giving the same result as your schematic here without the detrimental effects on clock networks.