What do you mean by "input characteristics"?
Textbooks and datasheets describe the behavior of MOSFETs using two graphs:
Output characteristics: \$I_D\$ versus \$V_{DS}\$ with \$V_{GS}\$ as parameter.
Transfer characteristic: \$I_{D}\$ versus \$V_{GS}\$ at a given fixed \$V_{DS}\$ value (this latter is chosen so that the MOSFET is in saturation region).
There is no "input characteristic" (such as the \$I_B\$ versus \$V_{BE}\$ curve of a BJT) because the other input quantity besides \$V_{GS}\$, namely \$I_G\$, is virtually zero at DC (and all these curves assume DC operations). Therefore it wouldn't make much sense to plot \$I_G\$ versus \$V_{GS}\$, unless you wanted to analyze leakage gate current, but I assume you are not interested in that.
So it is clear (also by a comment of yours) that by input characteristic you mean the transfer characteristic (TC). Note that the TC is plotted with a fixed drain-source voltage that guarantees that the MOSFET is in saturation for each \$V_{GS}\$ value on the horizontal axis. This is done because the TC is useful when the MOSFET is in saturation, i.e. when the output current depends solely on the input voltage (not considering "Early effect"), for example when you want to use the MOSFET as an amplifier and you need to draw a load line to design its bias circuit.
If you plot the TC for different values of \$V_{DS}\$ you get a family of TC curves. For example consider this circuit simulation with LTspice:
Plotting the TC for different \$V_{DS}\$ values you get:
As you can see, the more you increase \$V_{DS}\$ the more the curve resembles a parabola, as you would expect for the TC in saturation. Notice that this part shows a threshold voltage \$V_{th} \approx 4V\$.
Let's consider what happens if \$V_{DS}\$ is not big enough to drive the MOSFET in saturation for every \$V_{GS}\$ value, like in the lowest blue curve (Note: to present a more revealing plot I selected the curve corresponding to \$V_{DS} = 2V\$, whereas the lowest blue curve above corresponds to \$V_{DS} = 1V\$):
As you can see, in saturation region you get a quadratic curve, whereas in triode region you get a linear curve. Everything as expected, except that real devices don't have an abrupt change between the two regions and that the linearity of the triode region is not perfect because of the device not being ideal (SPICE models usually take into account these effects).
If you see in your simulation an abrupt departure from this behavior it could be that you tried plotting the curves outside the range of the voltages/currents admissible for your device. Notice that I limited the first plot to max 14A/20V which are the absolute maximum ratings for the device I chose. If you don't keep this in mind you will destroy the device (in real life) or get odd results (in simulations).
EDIT (in response to a comment and a question edit)
You ask why the "perfectly" linear curve for \$I_D\$ versus \$V_{GS}\$ in ohmic region is not exploited. Here is some insight:
Why do you need a linear characteristic between input (\$V_{GS}\$) and output (\$I_D\$)? Usually to use the device as a (linear) amplifier. But what are the conditions that allows to have that linearity? \$V_{DS}\$ must be held constant. Therefore to make an amplifier this way you have to insert a load in the output circuit and still keep \$V_{DS}\$ constant. You can understand that such a load cannot be a simple resistor (which is the simplest kind of load). Therefore you need a much more complex circuit (with other active devices).
On the other side, you can use the same MOSFET biased in saturation and get a decent linear amplifier: even if the behavior of the device is not intrinsically linear, but quadratic, there are linearization techniques (e.g. employ simple feedback schemes, like a resistor in series with the source terminal) that allow the overall amplifier to become more linear.
Best Answer
If one neglects the current that may flow through the \$V_{out}\$ connection, then both transistors will have the same current flowing through them. If the transistors have identical characteristics, then each transistor will have the same voltage \$V_{DS}=V_{GS}\$ across it's terminals, both will have the same \$g_m\$. This is true regardless of the applied voltage. If the current you draw from the output is small enough (relative to the current through the transistors), your output will be approximately 0.5 times your input. But that assumes your transistors are perfectly matched and the current drawn from the output is small enough.
The current through each transistor will change, but they should change equally. (Again, assuming we can neglect the current lost through \$V_{out}\$ connection. The problem however, is that you are using mosfets, which are (generally) enhancement mode devices. They do not conduct appreciably unless the gate-source voltage is at or above a threshold voltage. To get the transitors to conduct with 1V across both, will require a threshold voltage of 0.5V or less.
I don't really really know the details of your application, so the following suggestion may not suit your needs, but you may have better luck with very low voltages if you use identical JFETs configured with their source and gate connected. These will continue to conduct all the way down to 0V.
Or could you simply use resistors?
Edit: The reason why the voltage drop between the two transistors will tend toward equality is as follows. (We will assume there is no output current, at least for now.)
Hopefully you can see that if the transistors have identical characteristics, then if the current through each is equal, the voltages across them will be equal, and vice versa.