Powering a device through a GPIO pin is usually a bad idea. In the very low power regime, perhaps you could get away with it, but I would not recommend it unless you have very severe constraints.
You've already noted that you've checked that the ADC's requirement is lower than the pin's drive capability. That is typically what lot of people don't bother checking. If the consumption is within the required limits, then you may be fine on that count. However, make sure that any transient current requirements from the ADC are also contained within the GPIO drive capability. You would at the very least require reasonably heavy decoupling on the ADC supply. Remember the fact that the GPIO output isn't a low impedance supply line, and will be slower to respond to transient current requirements.
Secondly, since you're using an ADC, and at that an ADC that isn't built into a uC (which would be what you should be doing for very low power consumption), I'm presuming you have some requirements which aren't satisfied by the internal ADC. The GPIO, not being a supply line, and more importantly, being a GPIO of a microcontroller, will most definitely be contaminated by atleast the clock frequency of the uC, its harmonics, and possibly subharmonics. Since you're also going to be driving some substantial current through it, I would not be surprised if other effects are brought in as well. You may even end up seeing small components of your SPI/I2C/what have you in the supply, depending on which GPIO you use and how heavy the decoupling is. If ADC resolution and noise performance is important, then perhaps this is not such a good idea even if the GPIOs seem to be capable of driving the IC.
The high side FET is a much better bet, and is safer. You could also consider using any number of power related ICs which have Enable control, such as LDOs and the like. An LDO close to the ADC supply may also help with improving performance. Note, though, that this means your ADC will have to run at a slightly lower voltage. This will happen with a simple transistor switch as well, and with a low Rdson FET the effect will, admittedly, be much smaller, but it will exist.
One thing that you should note is that connecting an unpowered IC's digital lines to GPIOs of a powered uC is not a good idea. You will end up powering up your ADC through its digital IOs and cause strange, and potentially dangerous behaviour. Specifically, I would be surprised if your ADC did not respond even when OFF. This is capable of causing long term degradation, and eats into the advantage of power saving in the first place. In order to make it turn off well, you should use a level translating buffer for every digital line between the two with the ability to disable (tristate) the outputs. This can be done either using an EN pin, perhaps, or using a buffer with other mechanisms to disable (The SN74LVC1T45 tristates if the supply on one side is pulled to ground, for instance). Whether the scheme is useful depends on the consumption of the buffer in it's OFF state, the consumption in it's ON state, and the duty cycle (the fraction of time you want to turn it ON for), and the ADC consumption (900uA) that you can save by doing this. If you are very careful, you may be able to avoid the need for the buffers by tristating the uC IOs that are connected to the ADC before shutting it off, and thereby producing about the same effect.
Regular watchdog timers must be reset at some time before they time out. If you have a 100ms WDT you can reset it every 99.9ms or every 10us and it will never time out.
Window watchdog timers have a time window within which they must be reset. If you reset it too early or too late (from the previous reset) it will cause the processor to reset.
The purpose, if it is not obvious, is to help ensure that the code resetting the WDT is the intended code, operating in the intended fashion. Some kind of unforeseen condition that generates high-frequency WDT resets won't prevent the system from being reset.
Running a WDT from the system clock could be a bit of an issue- if the clock fails and if there is not an independent clock monitor circuit, bad things can happen. The independent clock for the WDT means that if the thing for some reason started running at 1/10 speed, the WDT would reset (but the window WDT would not).
Use both if you can.
As the page says, resetting the WDT with an ISR is generally bad juju (but may be acceptable if the ISR verifies the reset of the firmware is functioning before resetting the timer).
Best Answer
The watchdog has the task to monitor code execution and possibly to reset the CPU.
When the CPU is stopped, there's no reason for the watchdog to work or to be awaken.