Electronic – Using CPU heat to generate electricity

To directly answer your first question: No, not even close. A little more copper around a surface mount part isn't going to get rid of 11W of heat. No way.

One answer may be to parallel multiple FETs. Not only does that cut the total dissipation by the number of parts, but the dissipation on each FET is reduced by the square of the number of parts. So if one FET dissipates 10W, then two parallel FETs would dissipate 5W total, and each FET would dissipate only 2.5W.

That's in theory. In practise they won't share the load exactly equally, so you have to design for a bit worse than that per FET. The good thing about paralleling FETs is that they have a positive temperature coefficient. The Rdson goes up with temperature. This helps them ballance somewhat and prevents runaway of a single part, like could be the case with bipolar transistors.

Ultimately you have to decide what you really want. Switching 40A is going to make some heat. One way or the other you're going to have to deal with that. You can tell us you're space contrained all you want, but ultimately the physics will dictate a certain amount of space, surface area, forced cooling, or whatever. It may not be possible to meet all the constraints. Not all combinations of small size, high current, and low cost are possible.

Practically, what limits CPU speed is both the heat generated and the gate delays, but usually, the heat becomes a far greater issue before the latter kicks in.

Recent processors are manufactured using CMOS technology. Every time there is a clock cycle, power is dissipated. Therefore, higher processor speeds means more heat dissipation.

http://en.wikipedia.org/wiki/CMOS

Here are some figures:

Core i7-860   (45 nm)        2.8 GHz     95 W
Core i7-965   (45 nm)        3.2 GHz    130 W
Core i7-3970X (32 nm)        3.5 GHz    150 W

You can really see how the CPU transition power increases (exponentially!).

Also, there are some quantum effects which kick in as the size of transistors shrink. At nanometer levels, transistor gates actually become "leaky".

http://computer.howstuffworks.com/small-cpu2.htm

I won't get into how this technology works here, but I'm sure you can use Google to look up these topics.

Okay, now, for the transmission delays.

Each "wire" inside the CPU acts as a small capacitor. Also, the base of the transistor or the gate of the MOSFET act as small capacitors. In order to change the voltage on a connection, you must either charge the wire or remove the charge. As transistors shrink, it becomes more difficult to do that. This is why SRAM needs amplification transistors, because the actually memory array transistors are so small and weak.

In typical IC designs, where density is very important, the bit-cells have very small transistors. Additionally, they are typically built into large arrays, which have very large bit-line capacitances. This results in a very slow (relatively) discharge of the bit-line by the bit-cell.

From: How to implement SRAM sense amplifier?

Basically, the point is that it is harder for small transistors to drive the interconnects.

Also, there are gate delays. Modern CPUs have more than ten pipeline stages, perhaps up to twenty.

Performance Issues in Pipelining

There are also inductive effects. At microwave frequencies, they become quite significant. You can look up crosstalk and that kind of stuff.

Now, even if you do manage to get a 3265810 THz processor working, another practical limit is how fast the rest of the system can support it. You either must have RAM, storage, glue logic, and other interconnects that perform just as fast, or you need an immense cache.