Electronic – Verilog – Use integer constant to define signal width

system-verilogverilog

I have a module which takes two parameters, ParameterOne and ParameterTwo. I use their ratio a lot, so I gave it a name const integer Ratio = ParameterOne/ParameterTwo.

I want to have a signal whose width is this ratio, so I defined a signal logic [Ratio-1:0] wires. However, I get the error message Range must be bounded by constant expressions. This leaves me perplexed, as this range is bounded by a constant expression (I explicitly declare it to be const).

Does anyone here know why it's complaining about this code?

Best Answer

Although the terminology sounds similar, there are big differences between a constant expression and a const variable.

A constant expression is an expression whose operands are made up entirely of parameters and literals. Its value gets resolved as part of the compilation and elaboration process, before time 0.

A const variable is a variable that is written once at initialization, and you can never write to it again. The initialization can happen at any time based on the beginning of the variables lifetime, and can include the values of other variables that are not const. The earliest is at time 0 for static variables.

You should write this using a parameter or localparam`

localparam int Ratio = ParameterOne/ParameterTwo;

A localparam is just a parameter that cannot be overridden.

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You want to match the right hand side width with the declaration width to avoid tool warnings?

First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero:

wire [width-1:0] a_net = 1'b0;

If that generates a simulator/synthesiser warning your tools are outside of the Verilog spec. A common way to get around this is with the replication operator, which can take a constant width:

wire [width-1:0] a_net = {width{1'b0}};

Electronic – Please explain the following integer constant used in verilog

Even though the type indicator may be hexadecimal or decimal, the size indicator is always measured in bits.

8'h81

Since 81 is an 8-bit number in binary (1000 0001), it requires 8 bits. This is why the size is 8, even though the number is expressed in hex.

Also, size may be the bus size that the signal is driving (or part of it), even though the value itself may require fewer bits.

This is shown here:

16'd5

The decimal 5 only needs 3 bits (101), however, this value may be desgnated for a 16 bit bus:

wire [15:0] test;
assign test = 16'd5;

While verilog does pad smaller sizes, sometimes if you're concatenating, you want to specify each length:

wire [31:0] test;
assign test = {16'd5,16'd5};

In the last case:

32'h8f_32_ab_f7

32 bits are required to store the hexadecimal number, which is 1000 1111 0011 0010 1010 1011 1111 0111 in binary.

The hexadecimal is just the short way of writing the number, but the size is still 32 bits.

Best Answer

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Electronic – Parameterized net width in Verilog

Electronic – Please explain the following integer constant used in verilog

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