Have I understood that situation
correctly?
Yes - if some part of your output data is available later than other parts, you have to delay the other parts so they line up.
It's not a fudge, or a "bad" thing to do - it's just what has to be done to make the outputs right.
I could probably buffer the sync pulses too and delay them in the same way.
That's what I'd do. (EDIT: And as Yann reminded me, delaying signals can be very cheap in Xilinx FPGAs - 16 ticks can fit in a single look-up table + 1 more in the flipflop that's next to the LUT)
Or I could pre adjust the calculated memory address to compensate in advance.
That's another option, but will probably take more logic.
The Xilinx tools can't interface in real-time as far as I know, neither can ModelSim (used by Actel's Libero IDE)
I don't know about open source simulators, there are some rather exotic projects out there so it's possible there is something that could do this.
However, this may be you an answer you didn't ask for (I'll delete it if it's not helpful), but I would consider building your own FPGA board to do this or at least get started along the way towards it. I etched my first FPGA board and though it was very simple (the board not the process ;-) ), it taught me an awful lot quite quickly.
Pros:
- Cheap
- Jump right in at the deep end and learn all you need to know about the hardware considerations. Forces you to read most of the datasheets first, and write your own starter code, which IMHO is often better than the plug and play dev board approach to learning.
- Only put on the board what you need to.
- Get's you further towards your goal of a real working design with possibly the same effort/research as the figuring out how to simulate it all in real-time would.
Cons:
- Still need to buy a programmer, although cheap versions of the Xilinx/Altera programmers can be found on eBay.
- If PCB/signal integrity design and issues are not something you wish to focus on, then you may not be interested in much of the knowledge to be gained by doing it this way.
I understand the etching your own board is probably unnecessary, I only did it because I had the FPGAs there, was impatient and didn't want to wait 2 weeks for a PCB to arrive. There are extremely cheap deals out here for 2-layer boards, which would do to at least run your design (possibly at lower speeds than eventually desired - normally the minimum layer count for a high-speed FPGA design would be 4, but these are much more expensive)
Anyway, Spirit Circuits does a completely free 2-layer "bare bones" PCB deal (one a month, one design, no mask or silkscreen) which comes in handy for a one off design.
Also, for proper 2 and 4 layer cheap prototype boards, ITead and Seed Studio go as low as $10 for 10 boards (or possibly 5 at that price) services.
Best Answer
I'm not sure of any off the shelf test benches for what you want, and generally if there was one it would be expensive IP - somebody, most likely working for a company, would have to have made it.
In terms of what you could do, the best bet would be to write your own test bench to observe the control signals and save the raw RGB data output for each frame to a file. You can relatively easily write a test bench with a couple of counters synchronised with the Vsync/Hsync signals which for each valid pixel save the RGB data in a raw format (see
$fwrite
which is a Verilog file writing function).With the saved RGB data, you can view it using either software like MATLAB, or online viewers such as this website. Alternatively you could save the data in
ppm
image format directly from the testbench as @alex.forencich suggested in the comments which is a nice simple image format.While not ideal, this should provide a quick way to verify that the RGB data you are generating makes sense. I presume that what you want to test is that if code generating pixel data and feeding a VGA core of some description is feeding the correct data while you don't have hardware. If you are also working in class you will I presume have already been able to verify that the signal generation (VSync/HSync timings, data alignment, etc.) are working, so you can use that to set up and verify a test bench.