fpgasynthesisvhdl
The if-else and case statements are equivalent. The later maybe easier to read when we have a lot of possibilities being checked.
A conditional is supposed to infer mux in hardware. However, there is different between having a chain of 2-to-1 mux and a big n-to-1 mux doing the same thing in terms of propagation delay.
Is the if-else statement and case statement supposed to infer the same hardware? Or is there some difference in how they would be synthesized?
Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL circuit by the synthesis tool ?
The if-elsif-else construct infers a priority routing network:
simulate this circuit – Schematic created using CircuitLab
This corresponds to
if bool_expr_1 then
sig <= val_expr_1;
elsif bool_expr_2 then
sig <= val_expr_2;
elsif bool_expr_3 then
sig <= val_expr_3;
else
sig <= val_expr_4;
end if;
The case construct, on the other hand, infers a big ol' mux:
This corresponds to
case case_expr is
when c0 =>
sig <= val_expr_0;
when c1 =>
sig <= val_expr_1;
when c2 =>
sig <= val_expr_2;
...
when others =>
sig <= val_expr_N;
end case;
Obviously these are very simplified designs with only one value expression, resulting in one output.
Do consider the case of multiple nested if-else and mixing case-statements with if-else construct inside a process.
Per the above, you can see how they would nest/mix.
Also when to use which construct ?
Since if-else infers priority, it should be used when more than one input condition could occur. Using case, one the other hand, is appropriate when the inputs are mutually exclusive.
There are a number of nuances that come into play here.
Hence, your reset signal will update one delta cycle after clock. The "do work" portion of your process will see reset exactly one clock cycle after the clock cycle on which it was set. The VHDL simulation model is rock solid stable, so there will not be any uncertainty about how this particular process runs (like suggested by @MaximGi).
In a hardware design, you have put a flip-flop on reset and then fed that signal to other pieces of your design.
From a synthesis portability perspective, I caution you against putting any other logic in the same if condition as the clock. I would instead recommend re-writing your process as the following. Note your process is correct for simulation, it is just that some of the synthesis tools are fussy.
-- First process
process (clk)
begin
if rising_edge(clk) then
if reset= '1' then
-- do work
end if ;
end if;
end process;
Also there is no need for reset on this sensitivity list since rising_edge(Clk) will only be true on the exact delta cycle in which clock changes. You only need reset on a sensitivity list when you use asynchronous reset.
Best Answer
No: if-else is sequential; case is concurrent. A single if followed by an else will be equivalent to a two input multiplexer. An if followed by if else statements is equivalent to a series of two input multiplexers like this:
This is because the order you check the conditions of the if-else matters, i.e. you have priority.
A case statement, on the other hand is concurrent. Everything happens at the same time.