Electronic – VHDL “compile time” math

vhdl

I have a generic VHDL entity and I have this code:

--- in testbench
const bits : integer := 13;          -- number of bits
const pow: integer := 8192;          -- 2^bits
const squared : integer := 67108864; -- pow^2

In where I pass those 3 constants to the entity. What I would really like is something like:

--- in testbench
const bits: integer := 13;

--- in architecture (generic bits:integer)
const pow : integer := 2^bits;
const squared : integer := pow^2;

Since bits is known at synthesis time is there any way to do it without using hardware?

Best Answer

The VHDL power operator is **.

So your code should look like this:

-- in testbench
constant bits    : integer := 13;

-- in architecture
constant pow     : integer := 2**bits;
constant squared : integer := pow**2;

Related Solutions

Electronic – VHDL testbench variable clock/wave generation

You could use a procedure with an out parameter. The procedure can be declared in a package and called with different parameters for different 'clock' signals.

Here is an example of a clock_gen procedure from VHDL-extras:

subtype duty_cycle is real range 0.0 to 1.0;

procedure clock_gen( signal Clock : out std_ulogic; signal Stop_clock : in boolean;
  constant Clock_period : in delay_length; constant Duty : duty_cycle := 0.5 ) is
  constant HIGH_TIME : delay_length := Clock_period * Duty;
  constant LOW_TIME  : delay_length := Clock_period - HIGH_TIME;
begin
  Clock <= '0';

  while not Stop_clock loop
    wait for LOW_TIME;
    Clock <= '1';
    wait for HIGH_TIME;
    Clock <= '0';
  end loop;
end procedure;

The constant input period can be exchanged with a variable for simulation environments.

Usage example:

architecture rtl of my_entity is
  signal SimStop      : boolean     := false;
  signal my_clock1    : std_ulogic;
  signal my_clock2    : std_ulogic;
begin

  clock_gen(my_clock1, SimStop, 10.000 ns);
  clock_gen(my_clock2, SimStop,  6.666 ns);

  -- ...

  process
  begin
    --
    -- some stimuli
    --

    wait for 10 ns;
    SimStop := true;
    wait;
  end process;
end architecture;

Example to generate a waveform with an generic waveform:

type T_TIME_VECTOR is array(NATURAL range <>) of TIME;

constant myWaveform : T_TIME_VECTOR  := (
  -- generate "slow" pulse train
  20 * 250 ns,
  250 ns,
  -- generate "fast" pulse train
  50 * 10 ns,
  10 ns
);

procedure generateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIME_VECTOR; InitialValue : BOOLEAN) is
  variable State : BOOLEAN := InitialValue;
begin
  Wave <= State;
  for i in Waveform'range loop
    wait for Waveform(i);
    State := not State;
    Wave  <= State;
  end loop;
end procedure;

signal mySignal : BOOLEAN;

-- begin of architecture
generateWaveform(mySignal, myWaveform);

Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not).

Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a signal (port) -- if the value is known at compile time, the synthesis tool will evaluate the function at compile time and use the result. The only difference is that a generic is by definition known at compile time, while a signal may or may not be.

If the function needs to be evaluated at run time, then the synthesis tool will generate the logic required to do that, assuming that no non-synthesizable constructs have been used in the body of the function.

Best Answer

Related Solutions

Electronic – VHDL testbench variable clock/wave generation

Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Related Topic