I want to reset the variable v_count
to 0 at the rising-edge of input
port i_pulse_run
. But I get the following errors:
Error: Could not Implement register on this clock edge.
Error (10821): HDL error at PWM_Gen.vhd(85): can't infer register for
"CTRL:v_count[15]" because its behavior does not match any supported
register model.
How else can I reset the variable to 0. I want to reset it only at the
rising edge of signal i_pulse_run
.
Any suggestions are welcomed.
Thanks
LIBRARY IEEE;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_1164.all;
..
..
..
CTRL : PROCESS(i_Reset, i_Clock,i_pwm_pulse_run)
variable v_PWMout : std_logic;
variable v_intPWMvalue : integer range 0 to 8192;
variable v_updatePWMvalue : std_logic;
variable v_count : integer range 0 to 65535;
begin
if i_Reset = '0' then
-- Asynchronous reset
o_PWM <= '0';
s_PWMCounter <= 0;
v_updatePWMvalue := '0';
elsif rising_edge(i_Clock) then
-- Increment the PWM counter
if s_PWMCounter < i_PWM_Freq_Div - 1 then
s_PWMCounter <= s_PWMCounter + 1;
else
s_PWMCounter <= 0;
if rising_edge(i_pulse_run) then
v_count := 0; -- Error
end if;
if i_pwm_pulse_en = '1' AND v_count < i_pulse_count +1 then
v_count := v_count + 1;
end if;
end if;
..
..
end if;
end process CTRL;
Best Answer
D-Flops are only sensitive to the rising edge of one clock. In your case, you don't actually want it to change on the rising edge of i_pulse_run because the rest of your circuit is clocked off i_clock; what you should do is have another register saving the value of
i_pulse_run
on each clock cycle, and then when the input value ofi_pulse_run
!= savedi_pulse_run
, you are on the rising edge.