Electronic – VHDL: I can port map std_logic_vector to a signed or unsigned port, why

As others said, use ieee.numeric_std, never ieee.std_logic_unsigned, which is not really an IEEE package.

However, if you are using tools with VHDL 2008 support, you can use the new package ieee.numeric_std_unsigned, which essentially makes std_logic_vector behave like unsigned.

Also, since I didn't see it stated explicitly, here's actual code example to convert from an (unsigned) integer to an std_logic_vector:

use ieee.numeric_std.all;
...
my_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length));

Although in your example unsigned and signed are both arrays of the same element type std_logic, this is not the same as a subtype. A subtype is when one type is a limited subset of another type, for example:

subtype my_type is std_logic_vector(3 downto 0);
subtype eight_bit_int is integer range 0 to 255;

A feature of a subtype is that it can be automatically converted to and from the parent type, so I can do:

signal a : std_logic_vector(3 downto 0);
signal b : my_type;
signal c : integer;
signal d : eight_bit_int_type;

...

-- These should both work fine
b <= a;
c <= d;

If you want to connect differing types in a port map, you might have to use type casts or type conversions, or both. Using your example entity, you might write something like this:

signal a_actual : std_logic_vector(3 downto 0);
signal b_actual : std_logic_vector(3 downto 0);
signal c_actual : std_logic_vector(3 downto 0);
signal d_actual : std_logic;

...

-- Converting from std_logic_vector to signed or unsigned only requires a cast 
dummy_inst : dummy
port map(
    a => a_actual,
    b => std_logic_vector(b_actual),
    c => std_logic_vector(c_actual),
    d => actual
);

If you wanted to connect an input, for example b to an integer, you would have to use a type conversion and a cast, and the line would look like this:

b => std_logic_vector(to_signed(b_integer, 4)), -- 4 is the length of the port