I'm designing a VGA controller in VHDL and for video memory I decided to use SRAM memory. In order to manage the RAM I created a controller that must be interfaced with the VGA Controller. So far I have always programmed with sequential languages and so I have some problem in interfacing the two controllers.
For example: write a data in the SRAM takes a T time and when the controller has finished the operation it will trigger a READY signal. How do I make sure that the VGA controller wait for this signal? From what I have seen the VHDL WAIT statement can't be synthesized.
Electronic – VHDL SRAM Controller interface
sramvhdl
Related Solutions
The most straightforward thing to do (IMO) is to directly instantiate the device primitive in your VHDL. This way you are not relying on the tools to infer block RAM. In ISE, go to Edit -> Language Templates, and you will be able to bring up the template. (You will want to choose Spartan-3E, of course, although I think the primitive is the same in this case.)
The disadvantage of using the primitive, of course, is that your code is not trivially portable outside of the device family. (For block RAMs, this is not such a big deal since they are very similar across vendors and families.)
Another option is to use the Core Generator, which is perhaps more 'user friendly' to set up, but slow during initial synthesis. You can also generate an entire FIFO this way.
Perhaps someone can speak to methods of inferring block RAM.
READY - Used to insert wait states (controlled by memory and IO for reads/writes) into the microprocessor. (UNM document).
Id est, it's used by slow memory to tell the 8086 to pause until memory contents are ready to be read.
Best Answer
Simply count the cycles. There's no such "time" in synthesizable design. You have N cycles for write plus datasheet will tell K cycles to wait. That's it, use a counter until N+K reaches.