Electronic – Voltage to GPIO pins

Here is a block diagram of a 8051 variant. There are probably hundreds of different microcontroller architectures. Most are more complicated than the 8051 (which why I chose it, for its relative simplicity), and may have additional features such as DMA (Direct Memory Access), pipelining, caches, etc., but they all pretty much have to start with the basic components shown here: program memory, data memory (separate in a Harvard architecture, the same in a von Neumann srchitecture), instruction decode, accumulator(s) and/or register file, ALU, interrupt logic, and peripherals. (The 8051 does have a rudimentary instruction cache that can look ahead 6 instructions.)

The 8051 is a accumulator based machine that also has a set of four register files which are actually located in RAM. It is an 8-bit microcontroller, so the data bus is 8 bits wide.

Note that everywhere data must be stored off of the data bus, there are latches. Data can be transferred to and from the accumulator. The ALU (arithmetic logic unit) has two registers for storing its two operands, one of which can come from the accumulator and the other a data bus source (memory or peripheral register, for example), or both from the data bus (in which case the first is held in one of the ALU registers while the second is loaded). The B register is only used for the multiply instruction. Each of the ports has its own latch. The timers implicitly have registers within them.

When you configure the GPIO of the microcontroller to be low it's internal circuitry is set to sink current to VSS (or GND depending on how the pins are labeled on the part). The other end of the signal that you said is like another GPIO (maybe same MCU or maybe another one) that is set to a high level will be configured via its internal circuitry to source current from the VDD positive supply. So when they are tied together current will flow from the high GPIO to the low GPIO.

This condition is called contention and is not generally a very good thing for the GPIO pins. The current that can flow may far exceed the normal source and sink current ratings for the pins and could thus result in permanent damage to the parts from which the GPIOs are connected.

When in contention the wire that connects the two pins will go to some voltage level between VDD and VSS. The two GPIO circuits will each have some intrinsic resistance that limits the contention current to some level. These two intrinsic resistances will act like a voltage divider that in turn determines the contention voltage level.

As you can already surmise it is not a good idea to keep two GPIOs configured in a contention situation. If this is an accidental connection you should remove the short between the pins as soon as possible to prevent permanent damage to the devices. Otherwise you should always take design steps to prevent contention conditions from occurring. If it is unavoidable then your circuit design needs to include provisions for limiting the current flow to a level that is within design specifications for both of the GPIOs. This latter point is important because the source and sink specs of the two GPIOs may be different.