I am starting to work on some designs with MCU-based boards, or sometimes just looking at companies' products involving MCUs such as Espressif, Udoo, NXP… I have noticed a puzzling similarity between those MCUs, be it ARM Cortex, PIC or AVR family processors: the power-supply pinout.
I have looked up topics about the benefits of having multiple Vdd and Vss pairs, but what i find disturbing is their immediate proximity, i.e. they are next to each other. While there should be little problem with reflow oven or wave soldering in assembling processes, when it comes to SMD hand soldering this gets quite tricky for assembly or repair. It is really easy to short Vdd and Vss with the latter method and unless visible or checked after assembly/repair, one might badly damage its MCU or power-supply and start the board's design anew in the worst case scenario.
Hence my question really is: are there some benefits or silicon chip design constraints to why such layout is common place on our beloved MCUs? I have little to zero knowledge about silicon chip design or manufacturing. Or is this a way to ease the placing and routing of bypass capacitors?
Best Answer
As you say, it is a complete non-issue for high-volume manufacturing, which is where the vast bulk of such chips goes — and those are the customers that the chip makers pay attention to. Hobbyists don't buy nearly enough chips for them to even notice.
But yes, there are real advantages to this arrangement, both on the chip and on the board. Power and ground are distributed on the chip in metal layers on top of the silicon, and these connections interfere the least with signal connections if they run parallel to each other to the greatest extent possible, and this includes the external contacts.
On the PCB, you get the best performance out of the decoupling capacitors if their connections are as short as possible, and putting the pins on the chip next to each other makes this much easier. It also helps avoid congestion with signal connections here, as well.