Electronic – W5500 with POE functionality Link status ON with nothing plugged in

I resolved the problem, but it took re-manufacturing the board. The problem seemed to be with the routing and layer stack-up. The USB and Ethernet traces did not have correct impedance due to two reasons.

Firstly, the track geometry was not correct for 90 ohm (USB) and 100 ohm (ETHERNET) differential impedance. If your layout software does not support differential routing (eg: Altium does), then you will need to use something like SaturnPCB to calculate the track geometry and manually route the traces accordingly (I had to do this).

Secondly, and most importantly, the layer stackup was not correct to support USB and Ethernet high speed traces.The stack-up was TOP-INNER SIG-GND-BOTTOM and the high speed traces where routed on top layer. USB and ETH traces require a solid ground plane underneath and since this was not the case on my board it really messed up the signal integrity. Putting a solid ground plane (hence changing the stack-up to TOP-GND-INNER SIGNAL-BOTTOM) fixed the signal integrity issues.

I also cleaned up the placement of decoupling caps around the LAN9512 IC.

After these changes, the new board worked without problems. If you're using the raspberryPi to clock the LAN9512 (as B+ with LAN9514 does), then you also need to configure the Pi to output a clock signal. You can find info on this here: http://www.elektricks.net/raspberry-pi-compute-module-general-purpose-clock/ If you have a separate oscillator for the LAN9512 then ignore this paragraph.

Hope that helps!

Things that spring to mind:

• usually, you'd model your PCB trace as transmission line that has exactly the same characteristics on the top, as on the bottom layer. As such, it doesn't make much of a difference where on the length of a trace you put the via; so instead of having these "looking like boobies" vias right next to each other, I'd just offset them enough to keep them in the middle of your trace
• R51, C5 could as well be on Top Layer
• I don't know the frequencies of your xtal or CPU, but chances are that the 125 Mbaud of Gigabit ethernet won't be much impressed :) however, if you're nervous about coupling, you might want to consider the classical star-like multiple ground-plane architecture. I don't think this'll be necessary here – Gigabit Ethernet Network PHYs aren't exactly bleeding edge in 2016, so even with some interference, they should work.
• just looking at the part of the layout I see, I'd say it might be easier to route if you just rotated the PHY by 90° – but that might break down the moment the complexity on the "processor side" of the phy comes into play.
• I think your RJ45-magnetics layout is OK; I'd probably been lazy and just routed the two diff pairs that are at the right half of the transformer "down" from the connector's pins, and the left half "up"; but that wouldn't have saved you from the one pair that crosses the other if you're supposed to access the magnetic's pads only from one side (unless you fit two traces between adjacent RJ45 pins...) . Topology is not always your friend :/

Notice: 1GE has a baudrate of 125 MBaud, i.e. even if considering the first two sidelobes, you really shouldn't be worried about frequencies above 375 MHz. With FR4 (with specific epsilon), and a lot of laziness approaching formulas, the wavelength of that frequency is roughly \$\frac15 \frac{c_0}{375\text{ MHz}}= \frac 15 \frac {3\cdot 10^8 \frac{\text m}{\text s}}{3.75 \cdot 10^8\frac1{\text s}}\approx \frac4{15}\approx 0.27\text{ m}=270\text{ mm}\$, so a 2mm trace length difference is but 2.7° phase error ... I think you'll be fine, even with a bit of unelegant routing.