Electronic – What contributes gate charge in a MOSFET besides gate-source capacitance and gate-drain capacitance

Note that this is not a power converter but effectively a chip that uses a PFET to implement active rectification. As such, the current is intended to flow from the battery to the load when the switch is on. The FET is being used like a diode, making use of the inherent body diode of the part. The chip then turns on the FET to make the diode look more ideal when it should already be on. The chip will turn off the FET quickly when is sees SENSE go higher than Vin. If it didn't, the "diode" would conduct backwards.

The advantage of such a design is that the effective diode has very low forward drop, which is useful when it's in series with a battery since less of the battery power will be wasted. The drawback is that the overall diode has slow reverse recovery time, since the chip has to sense the reverse voltage and then actively shut off the FET. In this case the diode is used for power ORing, so a few µs reverse on time won't matter much.

In the IR document, they are driving the gate with a constant current. See the test circuit:

That is, they are delivering a constant amount of charge per unit of time. That's why they have the same shape: if charge is a linear function of time, then they are basically the same graph.

Notice that the flat spot on the gate voltage graph corresponds to the period where the drain voltage is decreasing (\$t_2\$ to \$t_3\$). Perhaps the best explanation of what's happening here is the next chapter in the IR document you reference, the section on \$dv/dt\$ capability:

Here, they are showing what happens when the drain has an increasing voltage ramp applied. But, this works in reverse, also. When the drain voltage is going down, there must necessarilly be some current in \$C_{GD}\$, in the opposite direction. This is because, as with all capacitors, a change in voltage must be accompanied with a current:

$$ I = C\frac{\mathrm{d}V}{\mathrm{d}t} $$

So as the MOSFET begins to conduct, and the drain voltage begins to decrease, some of the current from the gate driver must go into \$C_{GD}\$ to decrease its voltage. This is current that can't be going into \$C_{GS}\$ to increase its voltage. Thus, for as long as the drain voltage is going down, the gate voltage barely increases.

At \$t_3\$, the gate driver has managed to get the drain voltage about as low as it can go. After this point, the drain voltage doesn't decrease much with increased gate charge. Instead, you get a relatively slow decrease in channel resistance. So now the charge going into the gate is free to go mostly into charging \$C_{GS}\$, and the gate voltage can rise rapidly again.

I've not heard the term Miller plateau until now, but I have heard of the Miller effect, which is essentially what I just described, but in the general case for all amplifiers. So, I can see how one would reasonably call that flat region the Miller plateau.

Further reading: Vishay - Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance addresses this topic in more detail, and specifically uses the term Miller plateau.