I have been delving deep into digital logic and am trying to understand some memory architecture basics. I have started looking at data sheets to get a grasp on some real-world components and noticed something that I couldn’t find a clear explanation on.
In a data sheet for a 256×8-bit RAM module interfaced by I2C. There is all the things I would expect from an I2C device, however, there are also 3 pins for "Hardware Addressing". The data sheet explains:
"Three address pins, A0, A1 and A2 are
used to define the hardware address, allowing the use of
up to 8 devices connected to the bus without additional
hardware."
I obviously understand that this is for adding multiple devices, but I don't understand for what purpose? Not to mention if this is to signify an individual hardware device how much of a I2C pain it would be to sync. Maybe not?
I have included the data sheet and any clarity would be great.
DATASHEET (I know this is an old device, but I'm in it for the education)
Best Answer
These "hardware addressing" pins are not for addressing words in the RAM, but rather to select the address of the whole device on the IIC bus. The manufacturer realizes that you might want to have several of these chips on the same IIC bus, which means they each need a different IIC bus address. These pins allow you to pick one of 8 pre-defined addresses for each chip, depending on whether you tie these address lines high or low.
Some devices just use high and low on the address select pins. Other devices use high, low and open for trinary logic. 3 pins would give you 27 address possibilities. The TI INA219 only has two address select pins, but it uses 4-nary logic with high, low, connected to SDA or connected to SCL for a total of 16 address possibilities.