Electronic – What do you call the drawing which contains tracks, pads and drilling points of a PCB layer/side

Dynamic range refers to the difference between the maximum signal a system can handle and the noise floor for a specific system configuration. If the gain of the system is fixed, there is no difficulty with this definition. If the gain of the system can be varied, then the dynamic range becomes a function of the system gain. The use of the word "dynamic" means that it refers to the system capability in processing a signal at one point in time, in other words for one specific gain. Since the gain can only be varied statically, you cannot claim increased dynamic range by having a variable gain. For example, if you have a 10-bit A/D converter in the system, the dynamic range is generally taken as approximately 6 dB X the number of bits or 60 dB in this case. If you put a variable gain amplifier (say with 0 to 40 dB gain in front of this A/D converter, you can't claim the dynamic range of the system is increased by 40 dB. The advantage of the variable gain amplifier is the ability to set the system dynamic range over a given voltage range. For example, if the maximum input of the A/D converter is 10 volts, then the dynamic range of the system with the variable gain amplifier can be shifted from 10 millivolts to 10 volts with the amplifier gain set to 0 dB, to 0.1 millivolts to 100 millivolts with the amplifier gain set to 40 dB. In both cases, the dynamic range remains at 60 dB but the static range has increased to 100 dB.

Here is a better way: Don't!

The best way to document the design is by using the original code (VHDL, or Verilog). This is the most accurate, and will always be up to date. For simple designs, schematics might be more readable but that is not true for medium to large FPGA designs. At that size, schematics become hard to follow, large, cumbersome, difficult to modify/update, and are impossible to debug. So just don't use them.

When I have to document an FPGA design with schematics, I do it with Visio and make it more of a high level block diagram than schematics. Doing anything with more detail is a frustrating and fruitless task.

I would also argue that VHDL/Verilog are not difficult to follow. If someone can't follow them then the problem is the person, not the code. I have some FPGA designs that if printed out would take up about 800 pages of standard paper. That same design, if shown using schematics, would require 2,000+ large pages. It is easier to get proficient at reading VHDL/Verilog than to transcribe 800 pages of VHDL code into schematics (and then keep it up to date and accurate).