Main conclusions about this current loop, based on a drive-by analysis. The loop has way too much gain, and that gain is too variable over the span of output voltage. Also, it is doubtful that the bandwidth constraint forced by the INA282 is comprehended.
Let's go through each stage of the loop, in order of importance, to see how they look.
FET Driving Amp Stage
This is the most important stage in the loop since both the voltage loop and the current loop depend on it. Mess this stage up and there will be two problem loops for the price of one mistake.
The IRFP240 (Q1) is driven by a discrete amplifier made of the common emitter and common base stack-up of Q4 and Q2. It is almost a cascode amp, but because of R5 existence and modulation of Q2-B by Q1-S, isn't quite. Approximate gain for the stage is the ratio of impedance at Q2-C to the impedance at Q4-E. Dominant impedance at Q2-C is the JFET Q3 acting as current source with \$V_{\text{gs}}\$ = 0, while the dominant impedance at Q4-E ends up being \$r_e\$ of Q4.
JFETs like Q3 typically have variation in \$I_{\text{dss}}\$ of several mA unit to unit, but more important, channel impedance can vary by orders of magnitude as a function of \$V_{\text{ds}}\$. If \$V_{\text{ds}}\$ is ~2V \$R_{\text{ds}}\$ will likely be about 1kOhm. As \$V_{\text{ds}}\$ increases to ~10V \$R_{\text{ds}}\$ will increase too to something like 20kOhms. These parts don't really start to behave like current sources until \$V_{\text{ds}}\$ > 10V. For high output voltage (\$V_o\$) amplifier gain will be at the lowest and at low \$V_o\$ amplifier gain will be greatest.
BJTs like Q4 will have \$r_e\$ values from about 1 Ohm to 10 Ohms typically. It is not a directly specified parameter and will be a function of current and temperature. It may seem like R13 would swamp the wildness of \$r_e\$. Not so, since R13 is bypassed by C14, what is left is only \$r_e\$. For the calculations here, choose \$r_e\$ = 7 Ohms. Take the ratio of 1kOhm to 20kOhm by \$r_e\$ and find that over the range of \$V_o\$ amplifier gain could vary between about 40dB and 70dB at 1kHz. Too much gain, but mainly too much variation to be useable.
Here are some things to improve performance of this stage:
- Get rid of C10, it's putting a pole at a frequency that either nothing or a zero would be needed.
- Connect C12 and C14 to ZD2 cathode, instead of Q4-E, so as not to bypass R13.
- Increase value of R13 to reduce gain. Maybe as much as 300 Ohms.
- Get rid of R5, it's not doing anything for you either.
- Get rid of C3, it makes ripple rejection worse.
- Get rid of C6, it's not necessary.
- Replace Q3 with R4 and increase to 10kOhms to eliminate gain variation with changing voltage. Maximum dissipation in a 10kOhm should be ~ 0.25W, so use 0.5W part.
All this will allow the amplifier to produce a lower and more stable gain with a response flat out past 10kHz.
Current Sense Amp
IC1 is a diff amp stage that, along with R1, does an inter-domain conversion of current to voltage. A look at the title description at TI website shows the INA282 to be in the Zero-Drift family of amplifiers, which means that it is a switched capacitor part. That makes this a sampled data loop. So, in this linear regulator, the current loop will resemble that of a switching power supply because, Nyquist.
Schematic shows amplifier gain to be 50V/V which is 0.5V/A or -6dB. Gain will be flat out to about 10kHz or so and then, at around 100kHz, the gain and phase will crash like a load of bricks over a cliff because of the sampling. It will be undesirable to have the loop bandwidth be greater than 10kHz because of the rapid loss of phase at higher frequencies.
Since this stage has -6dB of gain, the rest of the stages combined can have a maximum of about 20kHz bandwidth. For example, at 1kHz the remaining stages combined could have a maximum gain of 26dB with a -20dB/decade rolloff for good loop performance.
Gain and Error Amp Stage
This stage starts with IC2D (TL074) as a diff amp, followed by IC2A as a non-inverting integrator. Since there is already a nice balanced diff amp stage (INA282 - IC1) this second diff amp is not needed. There will be a better way to do any gain and level shifting without using another diff amp, a way that would not require a bunch of tight tolerance resistors.
Non-inverting integrator for error amp. So many problems with non-inverting integrator use, stated categorically, loss of flexibility and options. The minimum attainable gain is 0dB, but usually, and this case is no exception, gain less than 0dB will be needed for some of the loop bandwidth.
Here's an idea. Turn IC2A and IC2D into inverting stages. Make IC2D a unity gain inverter and feed +2.5Vref into its non-inverting input through a 10kOhm resistor to take care of the offset. It will have better precision using 1% resistors than the diff amp using 0.1% resistors. Make IC2A an inverting integrator and feed I_Set into its non-inverting input through a 30kOhm resistor. You'll have to add a resistor in series with C9 to place a zero, but you'll have total control over where it is, plus the gain can go less than 0dB and maintain -20dB/decade rolloff until you need that zero.
Edit: About mapping I_Set to Io using inverting amps. Since IC2D would now invert the current signal, I_Set would need to be inverted too. This shouldn't be a problem since a micro-controller is being used to determine I_Set. But since most micros don't have negative outputs, an offset to the non-inverting input of IC2D will be needed. For the case IC2D has a gain of alpha, an equation for I_Set would be:
I_Set = offset - alpha(CSgain Io - offset + Vref)
where CSgain is the gain of the current sense amp (including R1), offset is the offset voltage applied to the non-inverting input of IC2D, alpha is the gain of IC2D, and Vref is any reference voltage applied to the current sense amp IC1.
For example if CSgain=0.5V/A and Vref=0V and offset=0.75V, I_Set would decrease from 1.5V to 0V as Io increased from 0A to 3A.
A Word About Power
\$V_o\$ of 0V to 50V with \$I_o\$ up to 3A is a lot of range for a linear. Let's say the Prereg voltage is 58Vand \$V_o\$ is set at 3V with a load current of 3A. Q1 \$V_{\text{ds}}\$ will be 55Vand its power will be 165W. Maintaining a junction temperature of 150C with an ambient temperature of 25C would require a total thermal resistance, junction to ambient, of 0.76C/W. Unfortunately 0.76C/W is lower thermal resistance than the junction to case thermal resistance of an IRFP240, so nothing short of refrigeration would help.
If you really want to supply that range of voltage and current, the preregulator output will have to track \$V_o\$ allowing Q1 \$V_{\text{ds}}\$ of 8V to 10V as head room. That would end up with 24W to 30W in Q1.
Best Answer
You keep trying to understand it "more electrically", but the problem is that pole dominance, and the pole concept itself, is strictly related to Laplace Transform (LT) theory, which is a strong mathematical theory.
Poles are not an "electrical concept" in itself. It is a concept that can be applied to any linear system, or any system amenable to be linearized usefully for the application at hand. They can be electrical systems, but also mechanical, thermal or systems in whatever field of application you may imagine where the LT techniques can be applied.
Chu already gave you a very simplified view of the concept in the time domain for an electrical system. I'll try to dumb down the things some more, but keep in mind that if you don't want to grok some math, it is really not possible to understand the concept in all its depth.
First of all, poles are related to how fast a system can react when it is excited, and the reaction time is related to how the system can store and release energy during and after the excitation.
An (idealized) system which cannot store energy has no reaction time, it reacts immediately to any stimulus it is subjected to (think of a pure resistive circuit, where resistors are ideal). Reaction time for electrical circuits, therefore, depends on elements that can store energy: reactive elements, that is capacitors and inductors (if we keep the things simple and don't consider mutual induction and/or distributed circuits).
Grossly simplifying, each independent reactive element contributes a pole to the circuit, and the number of poles of a system is called the order of the system. So a circuit with one cap and no inductors is a 1st order system. A circuit with a cap and an inductor is a 2nd order system (or two independent caps), and so on.
What does it mean "independent" element? Too complex for you, if you don't want to grok the math, so let's skip it. Very broadly, it means that the level of energy storage of one element is completely independent from the level of the other elements.
OK, now what do the poles do to a system? They describe the "reaction time***s***" of the system. Note the plural! A system that is excited momentarily (imagine a fast electrical impulse) reacts with a response that evolve in time and then dies off (if the system is stable).
This "impulse response" is made up of different components, each of which decays with a different time constant. Every pole contributes a different component with a different time constant. The time constant is a measure of how fast a component decays: the bigger the time constant, the slower the component decay (usually a component is considered zero after 5 time constants have elapsed, actually the decay lasts forever theoretically since it is exponential -- see Chu's answer for a simple math expression).
The impulse response of a stable system dies off after a while and the time it takes to die off gives you an estimate of the reaction time of the system: the time a system needs to stabilize into a new condition when the inputs are varied.
A dominant pole is a pole whose time constant is much "slower", i.e. bigger, than all the other time constants of the circuit, therefore the corresponding component is still observable after all the other, faster decaying, components have died off.
In other words, a system with a dominant pole behaves approximately like a 1st order system, i.e. a system that has a single pole.
In the end, the concept of pole dominance is a way to simplify a system: if a dominant pole exists, with some caveats, the system can be thought as a 1st order system, i.e. the simplest system imaginable that has a non-trivial time evolution.
The problem is that not every system has a dominant pole, so it can't be simplified that way. A technique used sometimes to simplify things is to add a compensating network in the circuit, i.e. a network containing at least one reactive element, in order to introduce a dominant pole in the system and thus allowing the simplification.
Of course, if you want to introduce a new pole in the system that has to be dominant, its time constant must be bigger of any existing pole (unless you do pole-zero cancellation, but that is a still nastier and more advanced technique), therefore you end-up slowing down the system. So it's often a kind of trade-off: you slow down a fast system in order to make it simpler, i.e. more manageable by the rest of the control chain. In the process you lose something (e.g. fast response or gain) in order to gain something else (e.g. stability or accuracy).
Note that my answer contains lots of hand-waving and gross conceptual simplifications, but everything I've said can be justified and expanded mathematically to give the exact definition and interpretation of what is a pole and what is a dominant pole. The problem is, as I've already said, that you can't escape the heavy math then.