Electronic – What does Nu (ν) prefix mean

BSC means "Basic Spacing Between Centers". This is often used if the reference lines don't refer to a physical point or edge, like in the case of the pins: the reference is in the middle of the pin, instead of one of the edges.

BSC SQ = BSC square, i.e. in both X and Y dimensions.

The abbreviation BSC is misused in the case of the package outline, and overall dimensions, as they are specified by physical edges which can be measured.

Usually a mechanical drawing of a package will show minimum and maximum values. BSC SQ must be regarded as nominal, so may deviate, but it doesn't say by how much.

One has to be careful when you are dealing with Wikipedia as evidenced by even the symbols you show above. While there are no "standards" that are commonly accepted, each design group usually adopts their own symbols, there is some meaning to the elements of the symbols. In particular the dotted line for the channel shows enhancement (i.e. the channel is "broken" before use. Depletion mode devices have a solid line because the channel exists before power is applied. The symbols above do NOT apply this rule evenly ...

There are a certain class of device that actually do not have bulk connections. They are called FD-SOI CMOS (Fully depleted - Silicon On Insulator). They are characterized by a layer of Si that is so thin that the depletion layer from the channel formation extends throughout it's depth. The bulk/Body connection goes away but the bulk/body is still there when the device is turned off. But the effect of it's non-connection is minimized (although noticeable in the transistor characteristics).

In every other case the bulk connection is there but is not shown simply as a shorthand way to draw quickly or to have less cluttered diagrams. Usually in that case it is understood what the bulk connection should be.

In the case of individual FETs (like Power Fets and HexFets) the bulk is connected to the source in package to minimize the number of leads. This can be done simply because the each die does reside as an individual die. When you have multiple transistors on the same substrate that is electrically connected one must always show the bulk in detailed designs.