Electronic – What does worst-case gate capacitance mean in a MOS transistor

The general formula for calculating capacitance is:

\$C=\dfrac{\epsilon \times A }{D}\$

Where A is the area of the capacitor's plates, and D is the distance between each plate. In terms used for designing a transistor, we would make the following substitutions:

\$ C = \dfrac{\epsilon \times W \times L}{t_{ox}} \$

Where W and L are the Width and Length of the transistor, and tox is the oxide thickness (distance between capacitor plates). If we were to scale all three by a factor of n, then we would see the following:

\$ C_{new} = \dfrac{\epsilon \times 0.7W \times 0.7L}{0.7t_{ox}} = 0.7\dfrac{\epsilon \times W \times L}{t_{ox}}\$

\$ C_{new}=0.7 \times C_{old} \$

This scaling doesn't end up changing the channel resistance, because both the width and the length are scaled. Examining the MOSFET drain current expression, we can see that the current (and effectively the channel resistance) is not affected by scaling both the width and length simultaneously.

\$ i_{D}=0.5\dfrac{W}{L}k_{n}^{(V_{GS}-V_{th})^2}\$

As a result, scaling reduces the total circuit capacitance while maintaining equivalent drive strength. Note the (used to) in the Wikipedia article - as the feature sizes have shrunk to about 90 nm, this relationship with oxide thickness has become more complicated.

Assuming that there is some finite rise time for your input signals, I think the worst case would be 00 to 11. You typically measure propagation delays from the 50% point of the inputs to the 50% point of the outputs, so the non-zero transition time of the inputs is important. You also have Miller effect coupling from the inputs to the outputs, which should not be ignored.

By the way, you have the body of Q3 tied to its source. In conventional, bulk CMOS technology the bodies of all NMOS transistors are usually tied to ground. Likewise, the bodies of all PMOS transistors would be tied to Vdd.