This answer is general to processors and peripherals, and has an SRAM specific comment at the end, which is probably pertinent to your specific RAM and CPU.
Output pins can be driven in three different modes:
- open drain - a transistor connects to low and nothing else
- open drain, with pull-up - a transistor connects to low, and a resistor connects to high
- push-pull - a transistor connects to high, and a transistor connects to low (only one is operated at a time)
Input pins can be a gate input with a:
- pull-up - a resistor connected to high
- pull-down - a resistor connected to low
- pull-up and pull-down - both a resistor connected to high and a resistor connected to low (only useful in rare cases).
There is also a Schmitt triggered input mode where the input pin is pulled with a weak pull-up to an initial state. When left alone it persists in its state, but may be pulled to a new state with minimal effort.
Open drain is useful when multiple gates or pins are connected together with an (external or internal) pull-up. If all the pin are high, they are all open circuits and the pull-up drives the pins high. If any pin is low they all go low as they tied together. This configuration effectively forms an
Note added November 2019 - 7+ years on: The configuration of combining multiple open collector/drain outputs has traditionally been referred to as a "Wired OR" configuration. CALLING it an OR (even traditionally) does not make it one. If you use negative logic (which traditionally may have been the case) things will be different, but in the following I'll stick to positive logic convention which is what is used as of right unless specifically stated.
The above comment about forming an 'AND' gate has been queried a number of times over the years - and it has been suggested that the result is 'really' an 'OR' gate. It's complex.
The simple picture' is that if several open collector outputs are connected together then if any one of the open collector transistors is turned on then the common output will be low. For the common output to be high all outputs must be off.
If you consider combining 3 outputs - for the result to be high all 3 would need to have been high individually. 111 -> 1. That's an 'AND'.
If you consider each of the output stages as an inverter then for each one to have a high output it's input must be low. So to get a combined high output you need three 000 -> 1 . That's a 'NOR'.
Some have suggested that this is an OR - Any of XYZ with at least 1 of these is a 1 -> 1.
I can't really "force" that idea onto the situation.
When driving an SRAM you probably want to drive either the data lines or the address lines high or low as solidly and rapidly as possible so that active up and down drive is needed, so push-pull is indicated. In some cases with multiple RAMs you may want to do something clever and combine lines, where another mode may be more suitable.
With SRAM with data inputs from the SRAM if the RAM IC is always asserting data then a pin with no pull-up is probably OK as the RAM always sets the level and this minimises load. If the RAM data lines are sometimes open circuit or tristate you will need the input pins to be able to set their own valid state. In very high speed communications you may want to use a pull-up and a pull-down so the parallel effective resistance is the terminating resistance, and the bus idle voltage is set by the two resistors, but this is somewhat specialist.
You don't need to exercise every peripheral, only those you use in your product. STM32 has clock gating and nearly all optional peripherals are disabled at startup. You only need to be concerned about peripherals that you enable in your production firmware.
As far as simultaneous operation is concerned, if you actually need that (it seems a different mode of operation from your production code which you say is blocking, so EMI may be different, too), you have 3 options: interrupts, DMA and preemptive RTOS tasks. Each of these is a topic in itself, but many examples exist, e.g. most examples that come with the standard peripheral library are interrupt-driven. Note that small implementation details may again result in very different performance (and therefore bus and peripheral activity). Making "all peripherals churn full-speed at the same time" is a very challenging task if you actually mean that literally.
On processors which use per-pin registers to select I/O functions, it is generally possible to route an output function to multiple pins without conflict; all pins will echo the same output. The effect of having multiple pins connected to an input is often unspecified; if e.g. a UART had I/O pins 3 and 4 connected to a UART, it might behave as though the UART was connected to an "AND" gate which took pins 3 and 4 as inputs, or it might behave as though it was connected to one pin and ignore the other, or it might connect both pins to the UART's input buffer through transistors that had a moderate amount of resistance, or it might draw extra current when pin 3 is high and 4 is low or vice versa, or it might do just about anything else imaginable. I don't recall having seen any particular guarantees that any of the STM32 family chips I looked at would favor any particular approach over any other.
A somewhat nicer design approach, used in some Microchip parts (perhaps some STM parts as well) is to have each I/O function include a multiplexer to select which pin it should accept input from, and have pin include a multiplexer to indicate the I/O function from which it should output data. Such a design makes it possible to have one pin feed multiple I/O functions, while simultaneously eliminating any ambiguities posed by conflicting configurations.