Electronic – What’s the practical difference of a wait process and a sense process

vhdl

All the VHDL-tutorials I've read mentions that one can use a sense process and a wait process, but I have been unable to grasp the difference.

That is:

Waitproc: process
    wait until clock ...
end process

Versus

Sense-proc: process (clock)
    if rising_edge(clock) then
    ...
end process

To me, these to seems do the same thing but obviously there must be a difference.

When should I use which one, and why?

Best Answer

In pure VHDL, there is no difference between a process with a sensistivity list (a,b,..x) and a process without one but with a 'wait on a,b,..x;' as its final line.

So no difference between:

  pFirst : process(a,b) is
  begin
    ...
  end process pFirst;

  pSecond : process is
  begin
    ...
    wait on a,b;
  end process pSecond;

You will almost always see the first form used because it is synthesizable. The wait statement is not.

Note that pSecond has the 'wait on' statement at the end of the process. At the start of simulation, all processes are carried out once, regardless of what they are sensitive to. The position of the 'wait on' statement in pSecond ensures that it does not pause for its sensitive signals until its end.

The second form is useful in testbenches where you want a non-synthesizable process to include time delays as well as sensitivity to signal(s). A process with a sensitivity list will not allow a 'wait for n us;' statement but one without a sensitivity list will.

So you can't do:

  pThird : process(a) is
  begin
    if falling_edge(a) then
      wait for 10 ns;
      cs  <=  not cs;
      wait for 2 ns;
    end if;
  end process pThird;

but you can do:

  pFourth : process is
  begin
    if falling_edge(a) then
      wait for 10 ns;
      cs  <=  not cs;
      wait for 2 ns;
    end if;
    wait on a;
  end process pFourth;

I find the latter very useful for writing bus master or bus slave models and so on.

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