I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762)
Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of the FPGA? Or is that a recipe for disaster?
It will be a single ended clock with a max. freq. of 125 MHz.
Or should I use a clock buffer to buffer the clock before each DAC clock input?
If so, is this a good clock buffer? (NB3N551)
Is there a better one I can use?
Edit: Sorry, I should have mentioned: All the DACs will be on a 5"x5" PCB connected through a short (few inches) ribbon cable to the FPGA board.
Edit2: If I can rephrase the question: If I can afford the room and cost of the clock buffers, are there any potential negatives? Or would that be the safe way to do this?
Best Answer
There won't be any problem (except for added power and cost) if you use a clock fanout buffer in this design, but I doubt if you actually need it.
Because your DACs are all located within 5 inches of each other you should be okay with a single receive buffer at the end of the ribbon cable. The fan-out from the receive buffer can be either a star with source-series termination for each fanning out line, as in apalopohapa's answer, or a daisy-chain with a split termination at the far end. The split termination would be a resitor to ground and one to Vcc, providing a Thevenin equivalent of R0 to VCC/2. R0 would match your nominal transmission line impedance, depending on your track geometry. Using a 50 Ohm characteristic impedance is common, but you will save power if you use a higher value like 75 or 100 Ohms.
With a maximum 5 inches between DACs you'd be talking about up to 1 ns difference in the update times between the DACs, out of a sampling period of 8 ns. The time difference would be very repeatable over time and temperature because it just depends on the track lengths between the chips.
N.B. Remember that however you buffer your clock signal, you'll also want to buffer your data signals to manage their delay to maintain correct sample & hold times at the DAC inputs.