Electronic – When does the reset on a 74HC164 Shift Register occur

digital-logic

I don't have a 74HC164 on hand to try and I'm not 100% sure from reading the datasheet.

If for example I've got a bunch of LEDs lit up from the outputs of the 164 and I pull the reset pin LOW will

A) all the outputs be immediately set to LOW as soon as I pull the reset pin low

or

B) all the outputs will keep their current state until the next clock pulse when all the outputs will be pulled low.

I'm waiting on some of these to arrive in the mail to experiment with but would love to be able to get my schematics in order while I wait. Thank you!

Best Answer

Synchronous timings are associated with a clock and in general asynchronous timings are not. (This can get confusing in terms of asynchronous events that are then aligned to a clock but that is not the case here).

Looking at the timing diagram:

HC164 Timing diagram

You can see that the firstclear event ensures the outputs are all low aligned with the falling edge of \$ \overline {CLR}\$.

Had this been a synchronous clear, then at the second event the outputs would have been taken low aligned with the clock (the blue line), but they are taken low (as before) when aligned with the falling edge of \$ \overline {CLR}\$

So the outputs will go low in response to the falling edge of clear and the clock has no effect on this.

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