For any given load, a switcher will transfer a given amount of energy thousands of times per second. This is how the buck regulator works.
Let's say your op-amp is switching at 10kHz (because it's a slow sort of device and will have slew rate problems compared to other devices). Let's also say you are aiming to deliver 5V across a 10 ohm resistor. Resistor power is 25/10 watts = 2.5 watts.
To calculate energy per switching cycle divide this power by frequency because power = joules per second. At 10kHz, the energy you transfer per switch cycle is 250\$\mu J\$.
This energy powers your load resistor but, if you removed your load resistor, this energy gets dumped into the output capacitor and its voltage rises a little (or a lot) higher than normal.
Let's say your output capacitor is 10uF - if suddenly it was imbibed with 250\$\mu J\$, how much would it rise in voltage?
We know that capacitor energy is \$\dfrac{C V^2}{2}\$ therefore we can calculate the voltage rise and this is: -
\$\sqrt{\dfrac{250\times 10^{-6} \times 2}{10\times 10^{-6}}}\$ = 7.07V.
It's a little bit subtler than this - in the above I assumed the capacitor was being charged with energy from a zero voltage state. In fact it already has 5V across it and this means that the previously stored energy + influx energy (from the inductor) is 125\$\mu J\$ + 250\$\mu J\$ = 375\$\mu J\$.
If you do the reverse math, the peak voltage on the capacitor becomes 8.66V i.e. 3.66 volts higher than the 5V rail.
You could put an argument together to consider the losses in the diode also - this may trim half a volt of the absolute peak voltage.
So, you either need to increase the capacitance a lot or, decrease the transfer energy by increasing the operating frequency. Modern switchers regularly operate at 500kHz and this means the energy per cycle reduces from 250\$\mu J\$ to 5\$\mu J\$ in this example.
Should this be the case (500kHz operation), the rogue energy from the inductor would make the capacitor's stored energy 130\$\mu J\$ and this means a peak voltage of 5.1 volts - probably quite acceptable for load dumping on a switcher.
Operating at higher frequencies requires faster silicon but, the ability to control load variations (and their repercussions), on a cyclic basis, means much tighter control of the output voltage.
This is just an example to see where you might be going wrong.
Just at first sight, your formula gives an energy (Joule), not power (Watt)...
If the "...custom equipment has an oscilloscope which is monitoring the voltage across the inductor and the current through it...", then the inductor losses can be calculated right out of the measured values (i.e. right from definition of average power) as:
\$ P_{losses} = \frac{1}{T} \int_0^Tv(t)i(t)dt \$, (average value of instant power during period)
where v(t) is the waveform of voltage across the inductor, i(t) is the waveform of current through it and T is period of these waveforms. Provided that the oscilloscope is a digitizing equipment, then, in principle, the corresponding voltage and current samples from within one period have to be multiplied, summed, multiplied by the sample interval and divided by the period (T) length.
For instance the trapezoidal integration method can be used:
If there are n equidistant samples (of \$ v_i, i_i \$, i = 1 to n) covering one period T, then the losses can be calculated as:
\$ P_{losses}= \frac{1}{(n-1)} \cdot (\frac{{v_1} \cdot {i_1} + {v_n} \cdot {i_n}}{2}+ \Sigma_{i=2}^{n-1} v_i \cdot i_i) \$
2015-04-12, \$ \textbf 1^{st} \$ appendix
As I already stated in the very beginning, your formula is not okay. At first, the T in it is superfluous (it is already incorporated in the duty cycle, D). Let's have a look at it a bit more closely. It can be rewritten (omitting the T, of course) as:
\$ P_{AC} = [D \cdot (V_{IN}-V_{OUT})-(1-D) \cdot V_{OUT}] \cdot I_{RIPPLE} = (D \cdot V_{IN}-V_{OUT}) \cdot I_{RIPPLE} \$,
but is it already okay?
You wrote "…Since the inductor has some AC losses from eddy current and hysteresis, I took the power during the charging period and subtracted the power during the discharge period and what would be left is the loss…".
In principle, this idea is right in my opinion, but:
- The voltage across L during \$ t_{ON} \$ (term with D multiplier) is:
\$ V_{L\_on} = V_{IN}-V_{PMOS\_SWITCH\_ON}-V_{OUT} \$,
not just \$ V_{IN}-V_{OUT} \$ (the PMOS switch contribution isn't negligible).
- The voltage across L during \$ t_{OFF} \$ (term with (1-D) multiplier) is:
\$ V_{L\_off} = -(V_{OUT}+V_{DIODE\_SWITCH\_ON}) \$,
not just \$ -V_{OUT} \$ (neither the diode switch contribution is negligible).
- If we presume both the above voltages as constants during their time intervals and the ripple current being "pure" sawtooth waveform, then value that must be used in the calculation on the place of current is \$ I_{RIPPLE}/2 \$ (i.e. its average value – it follows from the very first formula, because if v(t) = const., then it can be factored out the integral and the rest is the ripple current average value).
The resulting formula will be then:
\$ P_{AC} = [D \cdot V_{L\_on}+(1-D) \cdot V_{L\_off}] \cdot \frac{ I_{RIPPLE}}{2} \$
( \$ V_{L\_off} \$ is negative in relation to \$ V_{L\_on} \$, we have to measure both the voltages the same way, that's why the "+" operator is used in the formula)
It is questionable, however, whether the speculated presumptions (3) are "sufficiently" valid/met and how much they affect accuracy of the result.
Best Answer
It goes into the output capacitor. The pulse is short enough and the capacitor is large enough that it can be engineered not to significantly make the output voltage rise, maybe by few percent, as long as it is within limits so it's not too high. The output waveform also depends on how fast the regulator reacts to this via feedback loop and compensation as well.