Electronic – Where to put a spark gap for ESD protection–to an isolated “GND” or to protective earth

esdsparktransient-suppression

I am designing some PCBs for a system that runs on a fully-isolated DC power supply. I have three power inputs:

  1. Protective earth (connected directly to the line earth of a three-pin US 120V AC power outlet, and connected to the power supply only through EMI/RFI filter caps)
  2. 0VDC ("GND"), isolated from earth
  3. +12VDC, isolated from earth

My device has a large number of input and output lines. I would like to use spark gaps to provide some low-cost additional ESD protection.

My question is where should the spark gaps go:

  1. Between input/output pins and protective earth?
  2. Between input/output pins and 0VDC ("GND")?
  3. Between input/output pins and +12VDC?

My initial thought was to put them to 0VDC, which I am treating as ground for all of my digital logic, but I can't see any good reason to prefer that over +12VDC, since both are floating. Therefore, I thought, perhaps it makes sense to put the spark gaps between my pins and the protective earth.

What is the industry standard for protective circuitry when a protective earth is available? (Note that I am also putting class Y caps between the protective earth and 0VDC and between protective earth and +12VDC for EMI/RFI filtering.)

Best Answer

Typically (in my admittedly non-exhaustive experience), protective earth (the line earth) is connected to the chassis, and spark gaps go between device I/O and chassis ground.

This keeps ESD as far away (electrically) from the rest of your circuit as possible. ESD to chassis is by far the least damaging, as ESD won't (hopefully) mess with your circuit, and won't bounce the ground around.

I presume you have a metal chassis?