When the 8088 goes into hold, every output is tri-stated apart from HLDA (obviously), ALE and INTA. Given that the purpose of hold is to allow an external device to control the bus, like a DMA controller, what's the rationale behind ALE and INTA still being driven?
I think I partly know the answer to this:
If INTA (which normally isn't connected to another bus controller) wasn't driven high, it might float low and accidentally cause an interrupt vector to be placed onto the data bus causing contention.
If ALE wasn't driven low, it might float high and accidentally latch some spurious low-order address data, so that when the CPU came out of hold then A0..A7 would be incorrect. But this wouldn't matter, would it? As after exiting hold the next instruction's T1 cycle would cause the correct low-order address lines to be latched.
Is it simply that ALE doesn't NEED to be tri-stated?
Best Answer
Indeed, bus ownership is the key here. Asserting INTA grants an external device permission to drive the bus, but since the CPU is not allowed to drive the bus at this point, it is also not allowed to delegate that permission.
ALE goes to a single external component that we don't want to glitch -- it's not a bidirectional signal, and tri-stating it would only require adding a pull-down resistor.