Electronic – Why are PCIe Config Writes non-posted
pcipcie
In PCIe, why are config writes non-posted? Why can't they be like mem_wr which are posted?
Best Answer
This is most likely for reliability and transaction ordering purposes. The host can simply wait for a reply to know that the write transaction has gone through successfully, unlike posted writes which don't have any feedback. This can be very important when configuring hardware registers as things have to happen in a very specific order.
I know little about PCI, but it looks to me that the main thing about posted transactions is that you don't have control over them once they're initiated.
A bit like sending a message by mail (post!): once the message is in the mailbox it's beyond your control.
Other systems also use post, e.g. the Windows messaging system knows posting and sending. When sending a Windows message you're in control until the message has been handled, when posting you place it in the message queue, and that's it. No feedback, no acknowledging.
I think you are assuming here that the number of physical lanes is the bottleneck, and that if you only had more bandwidth then the logic inside the GPU would no longer be held back. I don't think that is really the case. To give you more bandwidth in one direction you need more area, power and resources dedicated to say receivers. Then your whole pipeline has to be designed to support this new double dataspeed. Not to mention a high speed serdes is a complex beast, so now you'd be making each piece even harder by trying to support both RX and TX.
When designers want to double bandwidth it's simple to just add lanes, just step and repeat. When PCI-SIG wants to increase the max speed for the next generation it's easier to just add features and increase frequency.
PCIe in particular is based on the concept of each lane pair being bi-directional. From the time it starts up and negotiates speed and TX/RX parameters, to later on for flow control. If you decided to take away one TX and change it to an RX, now another TX in a separate part of the chip would have to take over it's duties and it all gets pretty messy pretty fast.
Technically though if someone wanted to design a HS link system that allowed you to change your TX to RX for extra receive bandwidth it could be done. But it really would only make sense if pins were expensive because why add all the complexity to your system and design to support this when you could just add a few pins.
Best Answer
This is most likely for reliability and transaction ordering purposes. The host can simply wait for a reply to know that the write transaction has gone through successfully, unlike posted writes which don't have any feedback. This can be very important when configuring hardware registers as things have to happen in a very specific order.