Electronic – Why can’t I implement a frequency divider using a mux in this way

counterfpgamux

I found an interesting interview question for FPGA engineer online – Implement a counter with Mux, so I decided to try to do that. I tried to keep it simple and so implement a counter with two bits, so it can count only to 3 and then reset.

I came to a conclusion I need 3 multiplexers, two for each bit, and the other one to serve as a frequency divider for the clock (I'm sure there are other ideas, would love to hear them as well).
Note that I wanted this frequency divider to work at the falling edge of the clock.

Basically this is what I tried to do:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

I used a clock of 1Hz just so it won't be too fast (though maybe it doesn't matter?), With mux1 being the frequency divider.

The idea here is that the counter is like this:

So, since Q0 changes with every clock edge, I connected the clock to mux3. Since Q1 toggles every two clocks, I tried to design a frequency divider which will make sure that Q1 will toggle every two clock (clk1) falling edges.

I thought it would work well, but in a simulation (used Multisim for that, because I don't know how to simulate it work circuitlab, would love if you could show me how I can do that), I got a very strange result – the simulation just stopped. Here is how it looked (the output of mux1):

When I zoomed in at the falling edge (at 500ms) it looked like this:

So my questions are:

Why doesn't my frequency divider work?
Is this implementation of a counter even good, if that frequency divider worked? Is this even possible?

Best Answer

Think about what each part of your circuit does.

MUX3

All this is doing is saying if CLK1 is high, then output 1. If CLK1 is low, output 0. What is the purpose of this mux? Simply MUX3 = CLK1

MUX2

Again, if MUX1 is high, output 0, if MUX1 is low, output 1. So basically MUX2 = !MUX1

MUX1

What for example happens when CLK1 is low? It selects In0 of MUX1. In0 is simply the inverse of the output of MUX1.

So in other words MUX1 = !MUX1 - you've made an oscillator that will toggle at whatever the propagation delay of the not gate is. Uncontrolled inverter loops like this are almost never a good idea.

What happens if CLK1 is high? Well, you get MUX1 = MUX1, so basically the output will hold whatever state it had previously.

I think the theory of the interview question lies in the fact that a 2-input MUX is functionally complete - you can use multiple muxes to make any logic gate.

One of those is that a mux can be configured as an AND gate with one input inverted by simply tying the IN1 pin to GND. You can then simply use two of these to create an S-R latch.

Once you have an S-R latch it is very easy to build registers, and then counters.

Related Solutions

Electronic – CPLD best practice for resetting a counter

It sounds like you don't have an external reset signal to respond to, you just want to count to some number then go to zero as the next step. You could consider this a mod n counter, where n is one more than the maximum count in your counter.

So I'm not sure what you mean about "losing a signal" while doing the reset. If you had a 3-digit decimal counter and it rolled over from 999 to 000, you wouldn't consider it as "losing a signal", it would just be counting to the next value in mod-1000 arithmetic.

So if you do

always @(posedge clock) begin
    if (counter == some_number) begin
         counter <= 0;
    end
    else begin
        counter <= counter + 1;
    end
end

You'll have a counter that counts continuously in mod-some_number+1 arithmetic. Alternately you could say it counts to some_number, then resets to zero without ever "losing" a clock pulse.

If some_number+1 happens to be a power of 2, you don't even need the reset condition in your code. For example, for a mod-16 counter, you can just use a 4-bit counter, and the synthesized logic will count continuously and repeatedly from 0 to 15.

Electrical – 3 bit up/down counter using 2 flip flops

Technically, that's a 2-bit counter which uses the clock state as a pseudo-bit. If the only problem you have with it is that it appears to count down and you want it to count up, you can simply change the LED connections, as so

schematic

^{simulate this circuit – Schematic created using CircuitLab}

In the original, a high voltage produces a voltage across the LED/resistor and turns the LED on. In the new configuration a high produces no voltage and the LED is off, while a low voltage turns it on.

The requires that the logic you're using be able to sink currrent (suck it it) rather than source current (push it out), and you should be aware that if you're using the old 7400/74LS00 series ICs, they are not at all good about sourcing current, and the second approach is the preferred one if you want to get any brightness out of the LEDs.

With the LEDs changed you'll see that, in the original sequence, all 1's become 0's, and vice versa. Map out the new sequence and you'll see that it now counts up.

Best Answer

Related Solutions

Electronic – CPLD best practice for resetting a counter

Electrical – 3 bit up/down counter using 2 flip flops

Related Topic