Electronic – Why can’t I program a ZC706 (Zynq) board a second time over JTAG

The DONE pin in not used during JTAG programming and can be tied high:

If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can be tied High to a 330Ω resistor. (p57)

However, if Serial programming is used, then all the DONE pins should be tied together and the DriveDone should be disabled for all devices except the first:

It is important to connect the DONE pins for all devices in a serial daisy chain. Failing to connect the DONE pins can cause configuration to fail. (p135)

All devices except the first should disable the driver on the DONE pin. (p135)

If both are to be used, there are two options:

Alternatively, the driver can be disabled for all DONE pins and an external pull-up resistor can be added to pull the signal High after all devices have released it. (p135)

For debugging purposes, it is often helpful to have a way of disconnecting individual DONE pins from the common DONE signal, so that devices can be individually configured through the serial or JTAG interface. (p135)

In your case, I think connecting them and tying them all high while disabling the DONE pin is the best way to go.

All page numbers reference the User Guide

It's not really possible for the FPGA to exit the start up routine with a corrupted configuration as it confirms the CRC of the configuration after the complete configuration is loaded, but before it tries to start up. If it does not match, then the DONE pin stays low and you can check on what happened by reading the status bits over JTAG.

Since it seems like the configuration is always completing with the DONE pin released and your divided clock output is working, my guess is you may have a metastability issue or initialization issue in your design that you haven't caught yet.