Electronic – Why do serpentine traces (supposedly) entail decreased ESD immunity

ESD protection devices always have nonideal characteristics. When you're thinking about protecting an oscilloscope input, the relevant ones are leakage current and parasitic capacitance. If you're working with, say, a 1GHz scope, it only takes a very little bit of parasitic capacitance to significantly degrade the input signal, so oscilloscopes have to use low-capacitance ESD protection, and as little of it as they can get away with. That's likely to make such an input significantly more sensitive than something with lesser requirements on its inputs, such as a USB or charge connector on a phone.

Things that spring to mind:

• usually, you'd model your PCB trace as transmission line that has exactly the same characteristics on the top, as on the bottom layer. As such, it doesn't make much of a difference where on the length of a trace you put the via; so instead of having these "looking like boobies" vias right next to each other, I'd just offset them enough to keep them in the middle of your trace
• R51, C5 could as well be on Top Layer
• I don't know the frequencies of your xtal or CPU, but chances are that the 125 Mbaud of Gigabit ethernet won't be much impressed :) however, if you're nervous about coupling, you might want to consider the classical star-like multiple ground-plane architecture. I don't think this'll be necessary here – Gigabit Ethernet Network PHYs aren't exactly bleeding edge in 2016, so even with some interference, they should work.
• just looking at the part of the layout I see, I'd say it might be easier to route if you just rotated the PHY by 90° – but that might break down the moment the complexity on the "processor side" of the phy comes into play.
• I think your RJ45-magnetics layout is OK; I'd probably been lazy and just routed the two diff pairs that are at the right half of the transformer "down" from the connector's pins, and the left half "up"; but that wouldn't have saved you from the one pair that crosses the other if you're supposed to access the magnetic's pads only from one side (unless you fit two traces between adjacent RJ45 pins...) . Topology is not always your friend :/

Notice: 1GE has a baudrate of 125 MBaud, i.e. even if considering the first two sidelobes, you really shouldn't be worried about frequencies above 375 MHz. With FR4 (with specific epsilon), and a lot of laziness approaching formulas, the wavelength of that frequency is roughly \$\frac15 \frac{c_0}{375\text{ MHz}}= \frac 15 \frac {3\cdot 10^8 \frac{\text m}{\text s}}{3.75 \cdot 10^8\frac1{\text s}}\approx \frac4{15}\approx 0.27\text{ m}=270\text{ mm}\$, so a 2mm trace length difference is but 2.7° phase error ... I think you'll be fine, even with a bit of unelegant routing.