When
- the voltage produced by the uC is sufficient
- the switching time (resulting from the - limited - drive capability, maybe further limited by a series resistor, and the effective (!) gate capacitance) is acceptable
- there is no danger of 'backdrive' from the switching in the mosfet back to the gate to the uC (this can be a reason to include a gate series resistor)
When you are switching a 20mA LED or a 100mA relais using a TO92 logic-level mosfet I would drive the gate directly without hesitation (but I would check whether the gate voltage is sufficient) . When PWMming 10A motor I would not dream of doing so. In between there is of course a gray area, where careful consideration (and some smoking experiments) might save you a mosfet driver chip.
(edit - add "using a TXB0108 as fast mosfet driver")
The TXB0108 is a wonderful chip, but it drives its outputs in a very special way: a short pulse of relatively low impedance (50..100 ohm), then sustained by a relatively high impedance (4k). I could not find the duration of the pulse in the datasheet.
Your mosfet must have an low enough effective gate capacitance that it is sufficiently charged by the pulse. As ballpark value you could use the 70pF mentioned in the TXB0108 datahseet (minus PC stray capacitance, etc.).
The switching delays of the TXB0108 are up to ~ 10 ns with 15 pF load. This does not make me feel comfortable about reaching 100 ns with 70 pF.
The allowed voltage on a TXB0108 pin is 0.5 .. 6.5 V: there is margin beyond the supply range, with clamp currents of 50 mA. That might well mean that the chip is reasonably protected from latch-up and other unwanted effects that could be caused by backdriving. But note that this is in the infamous 'absolute maxima' section, NOT in the normal operations.
Management summary: the TXB0108 datasheet does not provide sufficient details, ballpark spec for the mosfet is < 50 pF effective gate capacitance, 100 ns might be achievable, but experiments will be needed to verify the design. Backdriving might not be a problem (specs look much better than an average uC pin), so the series resistor might not be needed, but again: insufficient data.
My only problem with the electrical example is regarding how the
system may couple its output back into its input. Is this a simple
case of simple feedback? How does simple feedback relate to capacitive
coupling?
An 1 Mohm 0805 resistor will have self capacitance of about 0.2pF and this, when applied in the feedback loop of an op-amp will reduce the gain from the 3dB point of 795 kHz. This means that the transimpedance amplifier you are designing will not work well at 10 MHz because there is too much capacitance - and that's just from a single surface mount resistor - imagine what capacitance there is between tracks and if this is not properly catered for by good PCB design, you'll be lucky to get 100 kHz flat operation from the above circuit.
The above is the case of negative feedback causing a signal to become smaller on the output due to parasitic capacitance.
It seems that the output would need some ripple voltage to begin with
that would be amplified.
The minutest noise will be enough to trigger oscillation if the feedback is positive. Noise is present in all components at temperatures above absolute zero.
Regards driving tracks having capacitance this is not directly related to the possible cause of oscillations and additionally the rule of thumb in your question doesn't take into account many, many factors such as the power capabilities of the driver, and the track dimensions and whether the track is terminated. At low frequencies there is no real rule at all.
Best Answer
For typical uses (very generally 10 - 100 V; 1-10 A, < 10 MHz), the physics of silicon mean that the capacitance of the FET structures (and parasitics associated with them) have values which have a more significant circuit effect than the inductance (generally associated with bonding wires and the package structure).
However, at high frequencies (certainly > 100 MHz); with certain DC/DC converters (low V, and high currents), the inductive parasitics can become significant and are critical. In these operating ranges, inductance in the gate lead can significantly affect the rate at which the transistor can be switched; inductance in the source can also affect this. inductance in the drain can cause large damaging voltages to appear between the internal transistor source and drain nodes, potentially damaging the device.