Suppose I have an NMOS. In the linear region the gate drain capacitance is modeled as \$C_{ox}\cdot w\cdot l(ov)\$ but it is modeled as zero when in the saturation region.
Electronic – Why is the gate drain capacitance in a mosfet zero when in saturation
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Related Solutions
The illustration is correct. VGS must be above Vth for the NMOS to be ON, otherwise it will be OFF. Therefore in your circuit the maximum possible voltage at the source is VDD-Vth, otherwise the NMOS would be OFF. Note that in your circuit VGS=VDD-(VDD-Vth)=Vth, so it is ON, but the voltage at the source cannot increase further because it would turn OFF the NMOS (and the source voltage would decrease, turning it ON again). It therefore comes to an equilibrium where VGS=Vth.
The fact that there is three NMOS instead of one doesn't change this situation, because all 3 NMOS have the same VGS voltage.
If you want to use an NMOS as a switch and have the full VDD on the load you should place it in the low side as in the following picture.
simulate this circuit – Schematic created using CircuitLab
At onset of saturation, inversion charge near drain decreases until it becomes zero, close to drain region. VD at which this happens is called pinchoff and drain current starts to saturate. At saturation regime (VD > VD-sat), pinchoff moves towards source leaving behind a depleted region; inversion charge drifts down conducting channel and is then injected into depletion region. ID will essentially remain constant because inside channel potential is fixed at VD-sat.
Please note that this is kind of "first-order" behavior of the MOS transistor, in reality the drain current in saturation regime is not constant and is affected by many other phenomena e.g. channel length modulation, velocity saturation, etc.
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Best Answer
This is mainly a question of definition. For sure there will be some capacitance between source and drain in saturation (--> Miller effect). Yet, it is true that Cgd is zero in saturation, at least according to a common definition.
When dealing with parasitic capacitances of MOSFETs the parasitics are divided into intrinsic and extrinsic capacitances. The intrinsic part is the part of the MOSFET with a source and drain region of zero width. For this intrinsic part the gate has a capacitive coupling to the channel. In the linear region the channel connects to drain and source, consequently the gate is capacitively coupled to drain and source. In the saturation region the channel is only connected to the source and separated from the drain by a depletion region. Therefore the gate to drain capacitance is zero.
The extrinsic part includes the drain and source areas. Overlap and fringing capacitances are the main reason for capacitive coupling between source and drain. They are present in the linear and saturation region.