Electronic – Why is the voltage across the capacitor constant

capacitorresistors

I've connected a 6V DC voltage source via a 1Ω resistor to a 1F capacitor. I was expecting the simulation to reveal a less constant t-vs-v graph: it would start at 0 and after a while stabilize at 6 volts. But it seems that the voltage across the capacitor begins at the source level and remains so. Two questions:

  1. Why is the voltage across the capacitor constant for the 10 seconds?
  2. (Secondary) Why isn't the current through the resistor I = V/R = 6/1 = 6 A (at least while the capacitor is being charged)?

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I'm making my first steps in electronics. Any feedback would be very helpful to me.

Solution. Thanks to everyone for the feedback. Lack of reputation doesn't allow me to upvote them, but all were very helpful to me. Turned out that I didn't check "use initial voltage", so while the initial voltage of the cap was set to 0, it wasn't being used:

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Circuit designed and simulated using SystemVision.

Best Answer

When you first apply a voltage across a capacitor, assuming the capacitor is discharged, it acts as a short, and thus will show 0 volts across it. However, depending on the value of R and C, the capacitor will eventually charge, and when it is "full" it will not allow any current to pass. It acts as an open circuit, meaning no current will flow (and thus, no current will flow through the resistor). Your simulation is showing the steady-state (after the capacitor has charged), so it shows the full 6V across it and no current flowing through the circuit. It seems that your simulation thinks your capacitor is fully charged when it begins. This is definitely not what I would have expected to see. I would have expected a voltage curve on the capacitor increasing up to around 6 volts in around 4.5 seconds, and then level off (and the current with an inverted version of the graph, eventually dropping to 0). Check the initial conditions of your simulation to make sure it doesn't treat your capacitor as charged on startup.