Why did x86 designers (or other CPU architectures as well) decide not to include it? It is a logic gate that can be used to build other logic gates, thus it is fast as a single instruction. Rather than chaining not and and instructions (both are created from nand), why no nand instruction?.
Electronic – Why is there no `nand` instruction in modern CPUs
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I'm not sure how far you want to go with this, but I'm afraid you may become frustrated when you find out how complex your design may become if you want it do something useful, no matter how nice and comprehensive it looked when you started.
Therefore I'm back with the suggestion to your previous question: the FPGA. There are complete so-called "soft processor" designs available free, but you can also build your own, starting from a 2-bit full adder if you want. (And that is what you want if you still have to learn VHDL.) Every FPGA manufacturer has development boards for its products, and there are also third-party boards, with a choice of on-board peripherals, like LEDs, character LCD, buttons, etc.
It's a perfectly valid technique, but unless you're sure the signals are glitch-free you need to do a little extra in order to prevent glitches being treated as spurious clocks.
This page describes clock gating with latches, from which I have lifted these diagrams:
The latches should be the "transparent" type.
In general any signal which is an "enable" can be turned into a clock enable if you account for the effects on timing skew.
(I spent about a decade in a startup built around software for automatically managing clock gates and timing in VLSI design!)
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http://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_nand_nd_instrs.htm : POWER has NAND.
But generally modern CPUs are built to match automated code generation by compilers, and bitwise NAND is very rarely called for. Bitwise AND and OR get used more often for manipulating bitfields in data structures. In fact, SSE has AND-NOT but not NAND.
Every instruction has a cost in the decode logic and consumes an opcode that could be used for something else. Especially in variable-length encodings like x86, you can run out of short opcodes and have to use longer ones, which potentially slows down all code.