I'm working on a home-brew CPU design, with the usual mix of parallel EEPROMs, static RAMs and registers, tri-stated onto a single 8 bit bus.
My /output-enable logic for three tristate-able chips on the databus is:
/Ken = /a /Ren = /a nor /b /Men = /a nor (/b nor /b)
Do I need to worry about the few nano-seconds during which more than one chip's /oe pin will be low, due to the differing number of gates?
Will current flowing out of a high output of one chip, into a low output of another chip, for less than 10ns cause damage?
If it would cause damage, how was this situation avoided in the 1970's-80's?
Update: Chips are: