Electronic – Will multiple chips outputing onto a bus for a few nanoseconds cause damage


I'm working on a home-brew CPU design, with the usual mix of parallel EEPROMs, static RAMs and registers, tri-stated onto a single 8 bit bus.

My /output-enable logic for three tristate-able chips on the databus is:

/Ken = /a
/Ren = /a nor /b
/Men = /a nor (/b nor /b)

Do I need to worry about the few nano-seconds during which more than one chip's /oe pin will be low, due to the differing number of gates?

Will current flowing out of a high output of one chip, into a low output of another chip, for less than 10ns cause damage?

If it would cause damage, how was this situation avoided in the 1970's-80's?

Update: Chips are:

Best Answer

There are a number of ways to create nonoverlapping enables for bus devices. Perhaps the simplest is to add the clock signal itself to your equations. Then, only one device at a time is enabled while the clock is high, and no devices at all are enabled while it is low. (Or vice-versa if you're using the rising edge of the clock to capture data.)

Normally, the output-enable function of most devices is fast enough that "wasting" half of each cycle in this way does not cause a timing problem. But if it does, one workaround is to modify the duty cycle of the clock as needed.