I'm a beginner who's become interested in Xilinx CPLDs. I get what CPLDs do, but I have no feel for the quantity of logic a macrocell can support or the sorts of situations where macrocells become inefficiently utilized.
Will someone shed some light, please?
EDIT –
Apparently I am not the only one; this is a dark art. However, if when using ISE one finds oneself out of macrocells, one can use the 'Exhaustive' fitter option and pretty much brute force a fit or show that there is no fit.
Best Answer
I wouldn't theoreticise (is that a verb?) too much about it. It depends so much on the kind of circuit that it's hard to predict accurately without any details. Get your feet wet and download the Xilinx ISE. Design a few circuits and the synthesizer will give you a report on the hardware usage.