I have been following the two Great Z80 Project guides and the only thing I don't get is the I/O. He uses a 6522 I/O V.I.A. and I don't quite understand the idea of I/O ports. So my question is, how do I hook more than one 6522 to the CPU so I can control more peripherals?
Electronic – Z80 I/O explanation
integrated-circuitz80
Related Solutions
You should pull the inputs /INT, /NMI, /BUSRQ, /WAIT and /RESET high with resistors.
/HALT is actually an output (including it in the list of inputs was my mistake) so it should be either high (usually) or low (only when the CPU is executing a HALT instruction).
Here is an example test circuit for the Z80. It connects all input lines except /RESET directly to +5V, which is OK if you don't ever want to use them (just make sure you connect the correct pins, as an output pin might not like being shorted to +5V!). When the CPU is running The LEDs should blink in a binary sequence, showing that the address is continually incrementing.
I would suggest using a CPLD or FPGA to interface the bus to something like a 16x8 LED matrix. Such a design would make it possible to switch among different display modes (e.g. it could have a mode that captures the address of /M1 cycles and would thus display a program counter in addition to the address bus). If you use a multiplexed LED, it would be good to have the CPLD/FPGA keep a count of what fraction of the time each light should be on, and adjust the brightness of the LEDs accordingly.
Another possibility would be to use a fast ARM chip to watch the bus and handle things in real time. It's possible for an inexpensive ARM7-TDMA to sit on a 1.19MHz 6502 bus and emulate a RAM chip (even without access to any signals other than A0-12 and D0-D7!); a 4MHz Z80 bus might be a little harder, but Z80 doesn't do things on absolutely every cycle the way a 6502 does.
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Best Answer
Great Z80 project goes on with I/O accesses, finding a way to bring 6522 to life every time the Z80 does an *I/O cycle. 6522's CLK2 pin is driven:
No I/O address decoding is done, which mean your single 6522 hogs the entire I/O address space. No other I/O device can be added to the bus, else you'll have a data bus conflict.
This is what chip select lines are for. He hard-wires the two CS lines (one high, the other low) to keep the single 6522 awake. If you want two 6522s on the bus, connect one of the CS lines (of each 6522) to a Z80 address line to select one or the other. And thanks for the memories.