Electronic – Z80 Simple Computer Troubleshooting: IORQ pin not going low

cputroubleshootingz80

I'm following the instructions at http://www.reocities.com/SiliconValley/2072/z80proj1.htm to build a "proof of concept" Z80-based computer. I have wired everything on my breadboard, and programmed the EEPROM with the following program (first instruction is at address 0):

LD A,#FF
OUT (#02),A
OUT (#03),A
LD A,#01
OUT (#00),A
JP #000A

This program should just turn on an LED wired to the I/O chip (a 6522 VIA) by setting a port output pin high; however, nothing is happening. I verified that the program in the EEPROM is the one posted here, and that I used the correct opcode values. I have a 1 Hz clock signal, and can "see" activity on the Z80 address and data pins with my logic tester. I also double-checked the wiring, but still nothing.

Working backwards, I noticed the I/O output pin connected to the LED never changes to high. I also noticed that the phase-2 clock on the I/O chip is always low (i.e. it doesn't oscillate); this explains the LED not lighting, since the I/O chip only reads on the rising edge. Per the instructions, I have connected this clock to the IORQ pin of the Z80 through an inverter; however, in my project, the IORQ pin is always high. From the Z80 datasheet, this pin should go low when a port is addressed, but this isn't happening. So I'm stuck, and not sure how to proceed from here.

Am I correct in thinking the IORQ pin should go low during OUT instruction? If so, what steps should I take to figure out why this isn't happening? Other theories on what may be wrong are also welcome.

Thanks in advance!

Best Answer

Yes, the /IORQ pin should go low when an OUT instruction is executed. The fact that yours isn't suggests that the program is crashing or not running at all.

There could be many reasons for this malfunction, such as a wiring error, faulty chip etc. I would start by checking to see if the CPU can work by itself. To do that I would:-

Remove the VIA and EEPROM. Check all wiring for shorts etc, and make sure the power supply and bypass capacitors are connected to the correct pins.
Tie all 8 data lines to ground via resistors (~1k each), to create a NOP instruction.
Power up the circuit and check that all input signals are correct (/INT, /NMI, /BUSRQ, /WAIT, /RESET should all be high)
Reset the CPU, then let it run and check for activity on /M1, /RFSH, /MREQ and /RD.

Assuming that test passes, change the opcode to OUT(#D3),A by raising all data lines to +5V except D5, D3 and D2. Then restart the CPU and look for activity on /IORQ and /WR.

If that doesn't work then the CPU is probably faulty (or a fake!).

If those tests pass then remove the resistors and put the EEPROM back in. You should get similar results. If you get activity on /M1, /MREQ and /RD (indicating that instructions are being read and executed) but nothing on /IORQ, check that the data and address lines are matched up between the CPU and ROM, and that the ROM is putting the correct data onto the bus.

If that works, then there must be problem in the VIA or its wiring.

Related Solutions

Electronic – Z80 control pins not reading a defined logic level

You should pull the inputs /INT, /NMI, /BUSRQ, /WAIT and /RESET high with resistors.

/HALT is actually an output (including it in the list of inputs was my mistake) so it should be either high (usually) or low (only when the CPU is executing a HALT instruction).

Here is an example test circuit for the Z80. It connects all input lines except /RESET directly to +5V, which is OK if you don't ever want to use them (just make sure you connect the correct pins, as an output pin might not like being shorted to +5V!). When the CPU is running The LEDs should blink in a binary sequence, showing that the address is continually incrementing.

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Electronic – How to z80 uses a 4-bit ALU and return results in a single clock cycle

The instruction actually ends at the end of T2 of the M1 cycle that reads the next instruction, as explained at z80.info

So, an instruction such as: SUB r can be broken down like this:

M1 / T1
M1 / T2 : read opcode
M1 / T3 : opcode is decoded as SUB r. A is loaded into op1 latch
M1 / T4 : r is loaded into op2 latch
------------
M1 / T1 : low nibble of substraction is calculated and stored in result low latch
M1 / T2 : high nibble of substraction is calculated and written to register file,
          result low latch is written to register file, 
          next opcode is read from memory

This overlapping scheme is only used if the operation writes to a register. If it writes to memory, no overlapping can be happened because that would collide with the M1 cycle trying to read an opcode.

Another example: INC HL. This increments a 16 bit register, so the 4-bit ALU must be used four times. INC HL has one M1 cycle that lasts 6 clock cycles. Its breakdown is this (the number of clock cycles for every machine cycle is taken from the Mostek MK3880 Z80 Technical Manual):

M1 / T1 :
M1 / T2 : read opcode
M1 / T3 : opcode is decoded as INC HL
M1 / T4 : L is loaded into op1 latch
M1 / T5 : low nibble of L is incremented and stored into result low latch
M1 / T6 : low nibble of H is loaded into op1 low latch,
          high nibble of L is incremented and written back to register file
------------
M1 / T1 : high nibble of H is loaded into op1 high latch,
          result low latch (new value of low nibble of L) is 
                               written back to register file
M1 / T2 : high nibble of H is incremented and written back to register file,
          read next opcode, etc...

ADD HL,DE : it lasts 11 clock cycles with the following breakdown: 4+4+3

M1 / T1 :
M1 / T2 : read opcode
M1 / T3 : opcode is decoded as ADD HL,DE
M1 / T4 : L is loaded into op1 latch
------------
M2 / T1 : E is loaded into op2 latch
M2 / T2 : low nibble of L+E is calculated and stored into result low latch
M2 / T3 : high nibble of L+E is calculated and written back to register file,
          low nibble is also written to register file
M2 / T4 : H is loaded into op1 latch
------------
M3 / T1 : D is loaded into op2 latch
M3 / T2 : low nibble of H+D is calculated and stored into result low latch
M3 / T3 : high nibble of H+D is calculated and written back to register file,
          low nibble is also written to register file

Best Answer

Related Solutions

Electronic – Z80 control pins not reading a defined logic level

Electronic – How to z80 uses a 4-bit ALU and return results in a single clock cycle

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