Equality 4 bit with 4 bit by IC 74181 (ALU)

It is possible that there is a "clock" line which must get an impulse for each of the 4 carry full adders until the right result is available at the output. If you have a clock pin somewhere feed it manually with at least 5 impulses or connect it to a continuous clock signal. Let the input lines be static and check if the carry is correct...

The basic idea is that the adder after the abext cells can do the heavy lifting needed for the first few operations, with some simple transformations of the inputs. Some options (not sure if these are all optimal):

• A + B → ia = A, ib = B, cin = 0
• A - B → hint: do you know how to convert B to 2's complement?
• A + 1 → ia = A, ib = 0, cin = 1
• A → ia = A, ib = 0, cin = 0
• A and B → ia = A and B, ib = 0, cin = 0 (just include the logic gate inside abext)
• The other 3 logic operations could be implemented similarly to "and", using ib = 0, cin = 0, or to balance things out you could have 2 of them have the logic gate in the ib path and set ia = 0.

A simple way to do this would then be to have 2 8-input multiplexers in each abext cell, and apply the inputs as specified in the list above: e.g., for the ia multiplexer, the inputs would be (A, A, A, A, A and B, A or B,...) when XYZ = (0,1,2,...). There are more optimized ways to do it, like by noticing that ia = A when X = 0, instead of duplicating A to the first 4 mux inputs.