FET with high current ( power JFET) low VGSoff

It's due to the way they operate - JFETs (and MOSFETs) are Field Effect Transistors, so the way they control the current is different (to a bipolar transistor - FETS are unipolar devices)

The gate to source impedance is naturally very high with these components - you can think of it a bit like squeezing a hose to stop the water flow - there is no actual current/water flow into the "hose".
A JFET is a depletion device - it starts out with a low resistance between drain and source, and then the gate-source is reverse biased to turn the FET off. Since the gate-source is basically a diode, you have almost zero current flow (just a bit of capacitance to charge up) With a JFET, if you foward bias the gate the impedance will be low, just like a normal diode.

With a MOSFET you can have both depletion and enhancement devices, due to there being a layer of oxide in between the bond and the substrate. This means the impedance is high no matter which way you bias the gate, since there is no DC connection between the gate and channel. The input impedance at the gate can be 100s of Megaohms, again a small capacitance is present which needs to be charged up in order to switch the MOSFET on.

Note that the above is a little simplified, there are operating conditions to watch out for as with other components (for example in a MOSFET the gate-source breakdown level is rather low, e.g. 10-15V. Also FETS are very sensitive to static discharge damage)

I would like to know if it is possible to produce an n-channel jfet connected in fixed bias configuration with a high gain of 200.

For your circuit, the product of the small-signal transconductance and drain impedance at the operating point set an upper bound on the voltage gain.

Using the numbers @Andy aka provides:

\$A_v < 20k\Omega \times 6.5 \frac{mA}{V} = 130\$

Since your drain resistor and load are in parallel with the small-signal drain impedance, your circuit gain must be less than this upper bound.

So, as a first step, you must select a transistor with maximum possible voltage gain quite larger than 200.